Senior System Power & Performance Architect (Datacenter)

NVIDIA AI

Eugene (OR)

On-site

USD 232,000 - 368,000

Full time

2 days ago
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Job summary

NVIDIA is seeking a Principal System Power Management and Performance Architect in the Silicon Co-Design Group to tackle ambiguous problems spanning workload behavior, silicon capabilities, firmware policies, and platform constraints. You will shape system-level power/performance features across generations and own integration strategies for HSIO, DVFS, and P-states.

You will lead boot/IST architecture, drive datacenter power telemetry strategies, and redefine boot/low-power entry with cross-IP

Qualifications

  • BS or MS in EE/CE, or equivalent experience.
  • 15+ years of system architecture, development, and validation experience with focus on power and performance-per-watt in datacenter/high-performance platforms.
  • Verifiable history of guiding architecture decisions that shipped across multiple silicon programs.
  • Extensive knowledge of HSIO power management, DVFS, P-states, and boot flows across IP/firmware/platform layers.
  • Strong fundamentals in low-power design and rack-level performance architecture.

Responsibilities

  • Define the multi-generation roadmap for system-level power and performance features with prototyping and cost/benefit trade-offs across segments.
  • Own architecture and integration strategy for HSIO power management, DVFS, P-states, and low-power features across product lines.
  • Lead system-level boot and IST architecture for complex multi-IP systems with large interaction space and critical failure modes.
  • Drive power management strategy at datacenter scale, including rack-level telemetry and platform state coordination.
  • Identify and redesign system-level processes that break under new product requirements and architect the next steps.

Skills

System architecture
Power management
Low-power design
Datacenter hardware
AI workflow discipline

Education

BS or MS in EE/CE

Job description

NVIDIA is seeking a Principal System Power Management and Performance Architect in the Silicon Co-Design Group to tackle ambiguous problems spanning workload behavior, silicon capabilities, firmware policies, and platform constraints. You will shape system-level power/performance features across generations and own integration strategies for HSIO, DVFS, and P-states.

You will lead boot/IST architecture, drive datacenter power telemetry strategies, and redefine boot/low-power entry with cross-IP

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