Senior Standard Cell Design Engineer

JRC Integrated Systems; Saint Paul (MN); On-site; USD 120,000 - 180,000; Full time

Benefits offered by this job

Competitive pay

Benefits package

Impactful DoD work

Collaborative culture

Career growth

Job summary

JRC Integrated Systems seeks a Senior Standard Cell Design Engineer to lead development of radiation-hardened microelectronics. You will architect LEAP standard cells, drive design‑tool chains, and collaborate with foundries on MPW runs to deliver robust, high‑reliability libraries in a fast-paced DoD-focused program.

You will have deep hands‑on experience in standard cell design, SPICE-based characterization, and modern node flows, with eligibility for a U.S. security clearance.

Qualifications

• Master’s degree with 2+ years of industry experience or Bachelor’s with 4+ years.

Responsibilities

• Design Radiation Hardened LEAP Standard Cell Libraries across advanced nodes.

Skills

Semiconductor design methodologies

Standard cell design

Circuit design

Layout

DRC/LVS

Timing analysis

Power integrity

Library characterization

Test‑chip designs

MPW execution

Education

Master's degree in engineering

Bachelor's degree in engineering

Tools

Virtuoso

Spectre

HSPICE

Liberate

PrimeLib

SiSmart

Job description

Who We Are (video)

At JRC, we tackle some of the toughest challenges faced by the Department of Defense (DoD) and other government agencies. Our expertise in engineering innovation and semiconductor technologies allows us to deliver mission‑critical microelectronics solutions, aerospace systems engineering, and cutting‑edge research and development. By joining JRC, you’ll be part of a team that supports strategic deterrence and defense missions, playing a crucial role in ensuring the safety and security of the United States and its allies.

Join JRC's Semiconductor Technology Team!

Join JRC’s cutting‑edge Semiconductor Technology team as a Senior Standard Cell Design Engineer and lead the development of next‑generation radiation‑hardened microelectronics. In this high‑impact role, you’ll drive the technical execution of our LEAP Standard Cell Library, shape proprietary simulation tools for radiation‑induced reliability prediction, and collaborate closely with foundry partners on advanced‑node designs.

You’ll architect and validate new standard cells across multiple technologies, optimize PPA under extreme conditions, support MPW test‑chip runs, and advance key automation and modeling capabilities. This role is ideal for an engineer who thrives at the intersection of device physics, circuit design, and reliability modeling.

We’re looking for someone with deep semiconductor design expertise, hands‑on experience in standard cell and library development, strong simulation and characterization skills, and eligibility for a U.S. security clearance. Experience with advanced nodes, RHBD techniques, memory design, and characterization tools is a strong plus.

If you’re excited about building resilient microelectronics that power mission‑critical systems, we’d love to meet you.

What You'll Do

• Execute the design and development of Radiation Hardened LEAP Standard Cell Libraries across multiple advanced foundry technology nodes.
• Generate and validate new standard cells and IP, including combinatorial logic, sequential logic, and power management cells.
• Leverage in‑house software and industry‑standard SPICE tools to calculate radiation‑induced error rates to ensure circuit resilience.
• Execute advanced library characterizations to optimize Power, Performance, and Area (PPA) in harsh environments.
• Collaborate directly with external foundry partners on Multi‑Product Wafer (MPW) runs and provide technical design support to customers.
• Contribute to the development of proprietary simulation software and automation scripts to improve reliability prediction.

What You Bring

• Master’s degree with 2+ years of direct industry experience, OR a Bachelor’s degree with 4+ years of experience.
• Must be eligible to obtain a U.S. security clearance due to the nature of defense‑related projects.
• Deep knowledge of semiconductor design methodologies and principles.
• Hands‑on experience with standard cell design, circuit design, and layout, and associated design tools (e.g. Virtuoso, Spectre, HSPICE)
• Demonstrated experience being involved in test‑chip designs and MPW execution.
• Proficiency in design flows including DRC/LVS, timing analysis, and power integrity.
• Extensive experience with simulation tools, specifically for library characterization.

Bonus Points

• Master’s degree with 5+ years of experience, or Bachelor’s with 7+ years in industry.
• Hands‑on design experience with GAA nodes (e.g., Intel 18A), including device architecture and design‑rule familiarity.
• Proven background in SRAM/NVM bitcell design and/or memory compiler development.
• Practical experience with Liberate, PrimeLib, and SiSmart for characterization and modeling.
• Expertise in RHBD for SEE/SEU mitigation, plus proficiency in C++ and scripting (Python/TCL) across advanced nodes (FinFET, GAA, SOI).

At JRC we offer...

• A competitive compensation package
• An exceptional employee benefits program, providing support for our team members' well‑being and success
• The chance to contribute to a high‑profile Department of Defense programs and make a positive impact
• A collaborative work environment where teamwork, creativity, and innovation thrive
• Opportunities for professional growth and development, helping you advance your career