Senior Staff Verification Engineer

ZipRecruiter; San Jose (CA); On-site; USD 120,000 - 180,000; Full time

Job summary

An innovative company in Silicon Valley is seeking a Senior Staff Verification Engineer to lead verification efforts for Smart Edge SoCs. This exciting role involves utilizing advanced verification methodologies such as UVM and Formal verification to ensure the integrity of ARM-based CPUs. The ideal candidate will have over a decade of experience in UVM verification, a strong background in test plan development, and proficiency in languages like C and SystemVerilog. Join a collaborative team dedicated to redefining digital security solutions and making a real-world impact in the tech industry.

Qualifications

• 10+ years of experience in UVM verification and environment development.
• Proficient in test plan creation and development using C, Assembly, and SystemVerilog.

Responsibilities

• Develop test plans and verification strategies for ARM-based CPUs.
• Coordinate with various teams across ASIC development stages.

Skills

UVM verification

C programming

Assembly language

SystemVerilog

Scripting (Perl, Python, Shell)

Coverage analysis

Post-silicon debugging

Education

B.E./B.Tech in EE, EECS, CS

M.E./M.Tech in EE, EECS, CS

Job description

Axiado is an AI-enhanced security processor company redefining the control and management of digital systems. Founded in 2017 with 60 employees, Axiado values collaboration, respect, innovation, and a passion for disrupting the status quo. We invite passionate individuals to apply for our open positions.

Job Description

The Senior Staff Verification Engineer will join a leading company in Smart Edge SoCs for network/system control, management security, and IIoT. The role requires prior experience with UVM verification and environment development.

Responsibilities include RTL SoC/Subsystem verification of ARM-based CPUs, utilizing verification methodologies such as UVM, Portable Stimulus, and Formal verification flows. The engineer will report to the Director of Engineering, Verification.

Key Responsibilities

1. Project Leadership
   • Develop test plans and verification strategies.
   • Verify micro-architecture design, RTL, and document findings.
   • Perform top-level and block-level verification, including performance, power, and use-case testing.
   • Support test program development, chip validation, and production readiness.
2. Team Collaboration
   • Coordinate with firmware, software, DV, FPGA, DFT, SoC integration, and backend teams across ASIC development stages.

Qualifications

• Over 10 years of experience in UVM verification and environment development.
• Proficient in test plan creation and testcase development using C, Assembly, and SystemVerilog.
• Expertise in RTL and gate-level design verification.
• Knowledge of coverage analysis, performance, and use-case verification.
• Experience with functional test vectors and post-silicon debugging.
• Proficiency in scripting languages such as Perl, Python, Shell.
• Knowledge of Power Aware verification is a plus.
• Work location options: Hyderabad, India; San Jose, USA; Taipei, Taiwan.

Academic Credentials

• B.E./B.Tech or M.E./M.Tech in EE, EECS, CS, or equivalent.

Additional Information

Axiado values diversity and is committed to attracting top talent. Located in Silicon Valley, we focus on real-world security solutions, emphasizing persistence, intelligence, curiosity, continuous learning, and mutual support. We are an Equal Opportunity Employer, basing employment decisions on qualifications and merit.