ASIC/SoC Verification Engineer (Senior Staff / Principle Level)

Delart; San Jose (CA); On-site; USD 90,000 - 150,000; Full time

Job summary

Join a forward-thinking company that is at the forefront of wireless technology innovation. As an ASIC/SoC Design Verification Engineer, you will play a crucial role in verifying cutting-edge designs for wireless connectivity solutions. This position offers the opportunity to work with advanced technologies, collaborate with a team of experts, and contribute to the development of high-quality products that impact the global market. If you are passionate about technology and eager to make a difference in the telecommunications industry, this role is perfect for you.

Benefits

Premium medical insurance

Dental insurance

Vision insurance

401k plan

Generous paid time off

Short/long-term disability insurance

Qualifications

• 7+ years experience in ASIC/SoC Design Verification required.
• Expertise in SystemVerilog and UVM methodology is essential.

Responsibilities

• Build functional verification infrastructure for ASIC modules.
• Develop automated test bench architectures and manage verification schedules.

Skills

ASIC Design Verification

Functional Verification

SystemVerilog

UVM

Verilog

Test Planning

Python

C/C++

Low Power Design Verification

Education

BS in Electrical Engineering

MS in Electrical Engineering

Ph.D. in Electrical Engineering

Tools

Synopsys EDA

Cadence EDA

Job description

4 days ago Be among the first 25 applicants

About the job
At Delart, we are a team of world-class engineers building the next generation of advanced wireless technologies that are deployed across the globe. Some of the biggest technology companies entrust us to build highly scalable, mission critical, communication and network solutions. Since our founding in 2017, we have participated in designing some of the most cutting-edge telecommunication and consumer products in the world.

JOB SUMMARY
As a member of our engineering team, you will work on the latest WLAN technology ASIC/SoC Design Verification (DV). Successful candidates will be participating in the verification of leading edge ASICs for Wireless Connectivity (Wi-Fi) SoC platform.

RESPONSIBILITIES AND DUTIES
As an experienced ASIC/SoC DV engineer, you will be responsible for building functional verification infrastructure, understanding the expected design functionality, developing test-plans as well as guiding the functional verification of complex ASIC modules/Subsystems/SoCs by deploying OVM/UVM until coverage goals are achieved in order to ensure the continued commercial success of our high quality products. Responsibilities will include all, or some, of the following:

• Develop automated and self-checking test bench architectures (including directed and random-constrained generation)
• Writing/debugging/maintaining behavioral models, monitors, assertions, scoreboards for self-checking test benches.
• Define and write IP/SoC verification plan based on product requirements; negotiating and executing functional verification plans according to coverage requirements.
• Delivering verification status reports and verification reviews. Logging bugs and tracking verification results, writing automated script to do post process verification reports
• Generating and maintaining verification schedules.
• Apply coverage-driven verification techniques at the functional, assertion and code levels.
• Work on verification of chip level functionality (mainly connectivity, programmability, power up/down, mode control, reset).
• SoC Chip level simulation and emulation, testing, verification, debugging and production chip test pattern generation
• Support FPGA prototyping and SoC validation

KNOWLEDGE, SKILLS, & COMPETENCY REQUIREMENTS

• Fully Understand ASIC Design Verification flow
• Must have expertise in understanding of code and functional coverage-driven verification closure and be able to set up and deploy verification strategies based on directed testing, randomization, assertions, and architectural performance testing to achieve coverage.
• Verification skills (test planning, test case development, coverage) is a must
• Working knowledge of Object-Oriented SystemVerilog principles including experience with VMM, OVM, or UVM.
• In depth knowledge of UVM methodology and SystemVerilog
• Expertise in verification and validation of complex SoC is required.
• Verilog/SystemVerilog RTL programming skills is required. Other programming skills (Python, C/C++, Perl, TCL, etc.) are plus.
• Family with Synopsys and/or Cadence EDA simulation and verification tools
• Previous working experience on 5G or WiFi SoC, Ethernet NIC, storage SoC are highly desirable.
• Experience of low power design verification (cpf and upf) is a plus

The following traits are highly valued:

• Knowledge of wireless communication system SoC functionality such as Wi-Fi, Bluetooth, UWB, 4G LTE and 5G NR is a plus
• Knowledge of 802.11 (11b/a/g/n/ax/ax/be) Wi-Fi protocol is a plus.

EDUCATION & EXPERIENCE

• Minimum years of applicable work experience for:
• Staff Verification Engineer: 7+ years
• Sr. Staff Verification Engineer: 10+ years
• Principal Verification Engineer: 15+ years
• BS/MS/Ph.D. in EE or related

Benefits
Delart offers competitive compensation and employee benefits, including premium PPO and HMO medical insurance coverage, dental, vision, FSA, life insurance, short/long-term disability insurance, a company-matched 401k plan, and a generous paid time off policy.

Help us redefine the future of connectivity. Apply today!

Delart is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees. We prohibit discrimination and harassment of any type without regard to race, color, religion, age, sex, national origin, disability status, genetics, protected veteran status, sexual orientation, gender identity or expression, or any other characteristic protected by federal, state or local laws.

Seniority level

Mid-Senior level

Employment type

Full-time

Job function

Quality Assurance

Industries

Technology, Information and Internet