Senior/Staff Silicon Quality & Reliability Engineer

Powerlattice Technologies Inc.; San Jose (CA); Hybrid; USD 140,000 - 190,000; Full time

Job summary

Powerlattice Technologies Inc. is seeking a hands-on Quality and Reliability Engineer to own company-wide quality, reliability, and design-for-reliability (DfR) initiatives.

You will bridge design teams, wafer foundries, and OSAT partners to establish rigorous quality gates and predictive models. This role collaborates across supply chains and manufacturing, leading qualification, risk mitigation, and lifecycle testing to extend product lifetimes of next-generation chiplet-based architectures.

Qualifications

• Advanced degree in Electrical Engineering, Physics, Materials Science or related field.
• 8+ years hands-on semiconductor process, quality management and reliability experience.
• Deep knowledge of semiconductor reliability physics and wear-out mechanisms.

Responsibilities

• Define process quality and reliability requirements with foundries and OSATs.
• Manage external suppliers through test vehicle qualifications and quality improvements.
• Oversee supplier quality, manufacturing excursions, and product return evaluations.
• Lead product qualification activities and risk-based material disposition.
• Develop predictive models for extrinsic and intrinsic failure mechanisms.
• Direct DfR initiatives to guide design teams on next-generation architectures.

Skills

Semiconductor quality

Reliability modeling

Cross-functional collaboration

Education

Advanced degree in EE, Physics, Materials Science

Tools

JMP

SPC

JEDEC

ISO 9001

AEC-Q100

Job description

Hybrid requiring 3 days a week onsite in the office

Reports To: Head of Engineering

About Us

Powerlattice is a well-funded semiconductor start-up company backed by well-known large Silicon Valley VCs. The company is working on the industry's groundbreaking chiplet solution for a fundamental shift in how high-performance chips get powered, paving the way for the next generation of AI and advanced computing.

About the Role

We are seeking a highly skilled and hands-on Quality and Reliability Engineer to own company-wide quality, reliability, and design-for-reliability (DfR) initiatives. You will bridge the gap between design teams, wafer foundries, and OSAT partners. Your mission is to establish rigorous quality gates, build predictive reliability models, and mitigate risks from development through high-volume manufacturing.

Key Responsibilities

Quality & Vendor Management

• Collaborate Cross-Functionally: Partner with foundries, OSATs, and internal teams to define process quality and reliability requirements.
• Drive Ecosystem Partners: Manage external suppliers through test vehicle qualifications and manufacturing quality improvements before tape-out.
• Monitor Quality Metrics: Oversee supplier quality, manufacturing excursions, and product return evaluations to ensure continuous improvements.

Qualification & Risk Mitigation

• Lead Product Qualification: Support internal product bring-ups, qualifications, and the disposition of excursion materials using risk assessments.
• Develop Lifecycle Models: Plan and execute stress testing with partners to build predictive models for extrinsic and intrinsic failure mechanisms.

Design & Methodology Strategy

• Direct DfR Initiatives: Conduct wear out reliability assessments and guide design teams to optimize next-generation product architectures.
• Standardize Quality Systems: Establish company-wide quality guidelines, qualification standards, and advanced frameworks to maximize product lifetime

Preferred Qualifications

Education & Experience

• Advanced Degree: PhD or MS in Electrical Engineering, Physics, Materials Science, or a related field.
• Proven Track Record: 8 years of hands-on experience in semiconductor process, quality management, and product reliability.

Technical Expertise

• Quality & Reliability Physics: Deep command of semiconductor physics, acceleration models, and wear out mechanisms (TDDB, BTI, HCI, EM, SM).
• Industry Standards: Direct experience with wafer-level reliability (WLR) tests, test structures, and quality standards (JEDEC, AEC-Q100, ISO 9001).
• Statistical Proficiency: Expert in quality and reliability statistics (e.g., JMP), SPC charting, and failure rate calculations across the bathtub curve.
• Failure Analysis: Strong knowledge of semiconductor defects, root-cause failure analysis (FA), 8D problem solving, and defect screening.
• Circuit Dynamics: Solid understanding of quality degradation mechanisms in logic, memory, and analog circuits.

Leadership & Soft Skills

• Communication: Excellent written, verbal, and presentation skills to interface with executive leadership and external vendors.