Senior Semiconductor Quality & Reliability Lead

Powerlattice Technologies Inc.; San Jose (CA); Hybrid; USD 140,000 - 190,000; Full time

Job summary

Powerlattice Technologies Inc. is seeking a hands-on Quality and Reliability Engineer to own company-wide quality, reliability, and design-for-reliability (DfR) initiatives.

You will bridge design teams, wafer foundries, and OSAT partners to establish rigorous quality gates and predictive models. This role collaborates across supply chains and manufacturing, leading qualification, risk mitigation, and lifecycle testing to extend product lifetimes of next-generation chiplet-based architectures.

Qualifications

• Advanced degree in Electrical Engineering, Physics, Materials Science or related field.
• 8+ years hands-on semiconductor process, quality management and reliability experience.
• Deep knowledge of semiconductor reliability physics and wear-out mechanisms.

Responsibilities

• Define process quality and reliability requirements with foundries and OSATs.
• Manage external suppliers through test vehicle qualifications and quality improvements.
• Oversee supplier quality, manufacturing excursions, and product return evaluations.
• Lead product qualification activities and risk-based material disposition.
• Develop predictive models for extrinsic and intrinsic failure mechanisms.
• Direct DfR initiatives to guide design teams on next-generation architectures.

Skills

Semiconductor quality

Reliability modeling

Cross-functional collaboration

Education

Advanced degree in EE, Physics, Materials Science

Tools

JMP

SPC

JEDEC

ISO 9001

AEC-Q100

Job description

Powerlattice Technologies Inc. is seeking a hands-on Quality and Reliability Engineer to own company-wide quality, reliability, and design-for-reliability (DfR) initiatives.

You will bridge design teams, wafer foundries, and OSAT partners to establish rigorous quality gates and predictive models. This role collaborates across supply chains and manufacturing, leading qualification, risk mitigation, and lifecycle testing to extend product lifetimes of next-generation chiplet-based architectures.