Senior Staff PCB Design Engineer

d-Matrix; United States; Hybrid; USD 180,000 - 240,000; Full time

Benefits offered by this job

Equity

Health care

Flexible time-off

Paid paternity leave

401k plan

Remote & hybrid work model

Team-building activities

Free food and snacks

On-site fitness center

Happy hours

Peer coaching & development

Job summary

d-Matrix is seeking a Sr. Staff PCB Design Engineer to lead the physical design of boards connecting its AI silicon to the world. You will own layout for 20+ layer PCBA boards, ensuring 112G/224G SerDes integrity and high-current delivery with minimal loss.

You will drive the design methodology, automate layout checks, and collaborate with power, ASIC, and manufacturing teams to scale hardware development with precision and speed.

Qualifications

• 10+ years of experience in high-speed, high-density PCB layout for servers, networking, or AI accelerators.
• BS in Electrical/Electronic Engineering or equivalent practical experience.
• Deep understanding of high-speed routing techniques (back-drilling, via-in-pad, skip-vias) and HDI/ELIC design.
• Proven track record routing 112G SerDes and complex DDR5/HBM interfaces.
• Proven ability to write and deploy SKILL scripts or use Allegro’s API to automate design audits and layout routines.
• Proficiency in Cadence Allegro Constraint Manager, including T-junctions, differential pair phase-tuning, and Z-axis delay matching.
• Experience establishing a Library Management System and standardized footprint/padstack creation processes.
• Familiarity with PLM/PDM integration for managing layout releases and ECO workflows.

Responsibilities

• Lead full-cycle layout for high-complexity AI accelerator cards (PCIe form factors) and system baseboards.
• Architect and manage the Constraint Manager (CM) hierarchy in Cadence Allegro, defining the source of truth for high-speed routing rules and electrical constraints.
• Develop automation scripts (SKILL, Python, or TCL) to streamline layout tasks, DRC checks, and reporting.
• Execute layout for ultra-high-speed interfaces including PCIe Gen5/6, CXL, and custom die-to-die (D2D) interconnects.
• Partner with Power Engineers on PDN strategy, including multi-phase VRM layouts and decoupling capacitor placement for high-TDP ASICs.
• Drive PCB stack-up definition, including advanced low-loss materials (Megtron 7/8) and hybrid build-ups.
• Serve as primary interface with fabricators and CMs to ensure DFM, DFT, and DFA requirements are met for high-yield production.

Skills

High-speed PCB layout

112G SerDes routing

Cadence Allegro

SKILL scripting

Python scripting

Allegro Constraint Manager

HDI design

DDR5/HBM interfaces

PLM/PDM integration

D2D interconnects

Education

B.S. in Electrical/Electrical Engineering

Tools

Cadence Allegro

SKILL

TCL scripting

Job description

• As Sr. Staff PCB Design Engineer, you will lead the physical design of the boards that connect d-Matrix's AI silicon to the world. Our "Corsair" platforms push the limits of signal density and power delivery, and you will own layout for high-complexity, high-layer-count PCBAs (20+ layers) — ensuring 112G/224G SerDes signals stay clean and thousands of amps are delivered with minimal loss
• Beyond hands-on layout, you will serve as custodian of our Design Methodology, driving the automation, tooling, and constraint management processes that let hardware development scale with precision and speed. You’ll partner closely with power, ASIC, and manufacturing teams, and have the autonomy to build layout infrastructure from the ground up
• Lead full-cycle layout for high-complexity AI accelerator cards (PCIe form factors) and system baseboards
• Architect and manage the Constraint Manager (CM) hierarchy in Cadence Allegro, defining the source of truth for high-speed routing rules and electrical constraints
• Develop automation scripts (SKILL, Python, or TCL) to streamline layout tasks, DRC checks, and reporting
• Execute layout for ultra-high-speed interfaces including PCIe Gen5/6, CXL, and custom die-to-die (D2D) interconnects
• Partner with Power Engineers on PDN strategy, including multi-phase VRM layouts and decoupling capacitor placement for high-TDP ASICs
• Drive PCB stack-up definition, including advanced low-loss materials (e.g., Megtron 7/8) and hybrid build-ups
• Serve as primary interface with fabricators and CMs to ensure DFM, DFT, and DFA requirements are met for high-yield production

Benefits

• Equity
• Health care
• Flexible time-off
• Paid paternity leave
• 401k retirement plan
• Remote & hybrid working model
• Work with world-leading engineers and researchers
• Team-building activities
• Free food and snacks
• On-site fitness center
• Happy hours
• Peer coaching & development

10+ years of experience in high-speed, high-density PCB layout for servers, networking, or AI acceleratorsBS in Electrical/Electronic Engineering or equivalent practical experienceDeep understanding of high-speed routing techniques (back-drilling, via-in-pad, skip-vias) and HDI/ELIC designProven track record routing 112G SerDes and complex DDR5/HBM interfacesProven ability to write and deploy SKILL scripts or use Allegro’s API to automate design audits and layout routinesProficiency in Cadence Allegro Constraint Manager, including T-junctions, differential pair phase-tuning, and Z-axis delay matchingExperience establishing a Library Management System and standardized footprint/padstack creation processesFamiliarity with PLM/PDM integration for managing layout releases and ECO workflowsKnowledge of PCB warpage mitigation strategies for large-form-factor ASICs and MCMs