Senior Staff Engineer Pre-Silicon Verification AMS

Infineon Technologies AG; Austin (TX); On-site; USD 118,000 - 162,000; Full time

Job summary

Infineon Technologies Americas Corp. in Austin, TX is seeking a Senior Staff Engineer Pre-Silicon Verification AMS to advance high‑performance IC verification in a collaborative R&D environment.

You will generate VerilogAMS/SystemVerilog models, develop mixed-signal testbenches with ADE Explorer and Xcelium, and verify device and system level requirements while collaborating with design and production teams.

Qualifications

• BSEE/ME or equivalent with 3+ years’ experience.
• Experienced with Cadence Virtuoso and Xcelium Tool Suite driven by the Hierarchy Configurations.
• Capable of creating schematics and generating a netlist for simulation.
• Good understanding of analog design techniques.
• Understanding the signal flow and boundaries between the analog and digital domains.
• Extensive experience in compiling, elaborating, and running mixed-signal simulations in both ADE Explorer and Xcelium.
• Solid understanding of analog Spectre simulation and associated AMS modeling of analog circuit blocks.
• Solid debugging skills in both the analog and digital domains.
• Conversant in Verilog, Python, C, C++ and capable of generating simple scripts.
• Experience with Microsoft Office Tools (Word, PowerPoint, Excel) and Unix/Linux shell commands and editors.
• Experienced with version control systems.
• Experienced with bug reporting and tracking systems.
• Works well with teams but is also a self-starter.

Responsibilities

• Generate VerilogAMS/SystemVerilog models and correlate results with schematic level performance using appropriate test benches.
• Coordinate with team members on the Design Entry, Development, and Implementation of custom AMS behavioral models and schematic netlisting for high-quality pre-silicon verification.
• Generate tests and perform verification of mixed signal designs utilizing ADE Explorer and Xcelium Suite.
• Generate simulation workbenches and interpret results to verify compliance with device- and system-level requirements.
• Contribute, support, and perform verification of DFT plans including support for digital scan chain testing.
• Verify functionality performances, as well as ATE and bench testability of Production ICs.
• Collaborate with teams on the Design, Development and Verification of Engineering and Production ICs.

Skills

VerilogAMS

SystemVerilog

Analog design

Digital design

Python

C

C++

Debugging

Scripting

Team collaboration

UDA/AMS knowledge

Verilog

Education

BSEE/ME or equivalent

Tools

Cadence Virtuoso

Xcelium

ADE Explorer

Spectre

Unix/Linux shell

Git/VCS

Job description

#WeAreIn for jobs that impact everyone's life. Build the future nobody’s dreamed of yet... are you ready to rethink the impossible? As a Senior Staff Engineer Pre-Silicon Verification AMS in our Research & Development team, you'll have the opportunity to merge creativity with your technical expertise by shaping the future of technology, driving groundbreaking projects, and bringing new ideas to life. Are you in?

Key responsibilities in your new role:

• Generate VerilogAMS/SystemVerilog models and correlate results with schematic level performance using appropriate test benches
• Coordinate with team members on the Design Entry, Development, and Implementation of custom AMS behavioral models and schematic netlisting for the purpose of performing high-quality pre-silicon verification of Engineering and Production ICs
• Generate tests and perform verification of mixed signal designs utilizing both Cadence’s ADE Explorer and Xcelium Suite of tools
• Generate simulation workbenches and interpret the results to verify compliance with both device-level and system-level requirements
• Contribute, support, and perform verification of DFT plans that may include support for digital scan chain testing
• Contribute, support and perform verification of functionality performances, as well as ATE and Bench testability of Production ICs
• Collaborate with various teams on the Design, Development and Verification of Engineering and Production ICs

Your Profile

You are best equipped for this task if you have:

• BSEE/ME or equivalent with 3+ years’ experience
• Experienced with Cadence Virtuoso and Xcelium Tool Suite driven by the Hierarchy Configurations
• Capable of creating schematics and generating a netlist for simulation
• Good understanding of analog design techniques
• Understanding the signal flow and boundaries between the analog and digital domains
• Extensive experience in compiling, elaborating, and running mixed-signal simulations in both ADE Explorer and Xcelium
• Solid understanding of analog Spectre simulation and associated AMS modeling of analog circuit blocks
• Solid debugging skills in both the analog and digital domains
• Conversant in Verilog, Python, C, C++ and capable of generating simple scripts
• Experience with Microsoft Office Tools (Word, PowerPoint, Excel) and Unix/Linux shell commands and editors
• Experienced with version control systems
• Experienced with bug reporting and tracking systems
• Works well with teams but is also a self-starter

#WeAreIn for driving decarbonization and digitalization.

As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener. Are you in?

We are on a journey to create the best Infineon for everyone. This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant´s experience and skills. Learn more about our various contact channels.

Driving decarbonization and digitalization. Together.

Infineon Technologies Americas Corp., is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex (including pregnancy, childbirth, or related medical conditions), gender identity, national origin, ancestry, citizenship, age, physical or mental disability, legally protected medical condition, family care status, military or veteran status, marital status, domestic partner status, sexual orientation, or any other basis protected by local, state, or federal laws.

Employment at Infineon is contingent upon proof of your legal right to work in the United States under applicable law, verification of satisfactory references and successful completion of a background check and drug test, and signing all your on-boarding documents.

In some instances, if applicable, U.S. export control laws require that Infineon obtain a U.S. government export license prior to releasing technologies to certain persons. This offer is contingent upon Infineon's ability to satisfy these export control laws as related to your employment and anticipated job activities. The decision whether or not to submit and/or pursue an export license to satisfy this contingency, if applicable, shall be at Infineon’s sole discretion.

Infineon Technologies takes data privacy and identity theft very seriously. As such, we do not request personally-identifiable information (PII) from applicants over the internet or electronically. Please kindly refrain from disclosing your PII electronically during the application process or to unauthorized websites that may purport to be Infineon or any of our affiliates.

In the United States, it is required to disclose a salary range to applicants. The Wage range that the company expects to pay for a qualified candidate in the United States is:

Andover, MA & Warwick, RI: Minimum of $117,840.00 Salary per year/ Maximum of $162,030.00 Salary per year

In addition, all employees will be eligible to participate in an incentive plan.