Senior STA Timing Closure Engineer (Hybrid)

Tenstorrent Unlisted/Referral Jobs; Santa Clara (CA); Hybrid; USD 100,000 - 500,000; Full time

Job summary

Tenstorrent is seeking a mid- to senior-level Physical Design Engineer with a strong background in static timing analysis to help converge multi-million-gate designs. The role is hybrid and can be based in Austin, TX, Fort Collins, CO, or Santa Clara, CA, with offers aligned to experience level.

You will work across cross-functional teams to drive timing convergence, signoff, and tapeout, using Python/Perl/Tcl for automation and scripting in a cutting-edge AI hardware context.

Qualifications

• 8+ years of experience in STA, timing closure, and advanced-node design implementation.
• Experience with timing flows, constraints, clocking, CDC/RDC, derates, guardbanding and final signoff.
• Strong ability to write and debug SDC constraints, develop closure strategies and analyze worst-case corners.

Responsibilities

• Drive timing convergence across blocks, partitions, sections, and top-level designs; generate timing models and publish results.
• Analyze timing violations, develop fixes, debug timing-flow issues, and drive progress toward tapeout.
• Develop and validate bottom-up constraints with Design and DFT teams on methodologies and closure requirements.
• Use Python, Perl, and Tcl for automation and flow development; familiarity with SPICE, PNR, placement, CTS, routing, DFT, or AI automation is a plus.

Skills

STA expertise

Timing closure

Advanced-node design

Tools

Python

Perl

Tcl

SPICE

PNR

CTS

DFT

Job description

Tenstorrent is seeking a mid- to senior-level Physical Design Engineer with a strong background in static timing analysis to help converge multi-million-gate designs. The role is hybrid and can be based in Austin, TX, Fort Collins, CO, or Santa Clara, CA, with offers aligned to experience level.

You will work across cross-functional teams to drive timing convergence, signoff, and tapeout, using Python/Perl/Tcl for automation and scripting in a cutting-edge AI hardware context.