Physical Design Engineer, Timing

Tenstorrent; Santa Clara (CA); Hybrid; USD 100,000 - 500,000; Full time

Job summary

Tenstorrent is seeking a mid- to senior-level Physical Design Engineer with 8+ years of experience in STA, timing closure, and advanced-node design implementation. Embrace a hybrid role with multiple locations and collaborate across teams to drive tapeout success.

You will write and debug SDC constraints, develop ECOs and closure strategies, and apply Python/Tcl scripting to automate flows while engaging with SPICE/PNR/DFT areas as needed.

Qualifications

• 8+ years of experience in STA, timing closure, and advanced-node design implementation.
• Experienced with timing flows, constraints, clocking, CDC, RDC, derates, uncertainties, guardbanding, and final signoff.
• Skilled in writing and debugging SDC constraints, creating ECOs, developing closure strategies, and analyzing worst-case corners.
• A strong collaborator and communicator who can drive results across distributed, cross-functional engineering teams.

Responsibilities

• Drive timing convergence across blocks, partitions, sections, and top-level designs; generate and validate timing models and publish results.
• Analyze timing violations, develop and propagate fixes, debug timing-flow issues, and keep execution progressing through tapeout.
• Develop and validate bottom-up constraints while partnering with Design and DFT teams on methodology updates and closure requirements.
• Use Python, Perl, and Tcl for automation and flow development; experience with SPICE, PNR, placement, CTS, routing, post-route optimization, DFT, or AI-based automation is a plus.

Skills

STA

Timing closure

Clocking

SDC constraints

ECOs

Python

Tcl

Spice

PNR

DFT

AI-based automation

Tools

SPICE

PNR

DFT

AI-based automation

Job description

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.

Tenstorrent is looking for a mid- to senior-level Physical Design Engineer with a strong background in static timing analysis (STA). In this role, you will help converge multi-million-gate designs on advanced process nodes and partner with cross-functional teams through final signoff and tapeout.

This role is hybrid, based out of Austin, TX, Fort Collins, CO, or Santa Clara, CA.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• A physical design engineer with 8+ years of experience in STA, timing closure, and advanced-node design implementation.
• Experienced with timing flows, constraints, clocking, CDC, RDC, derates, uncertainties, guardbanding, and final signoff.
• Skilled in writing and debugging SDC constraints, creating ECOs, developing closure strategies, and analyzing worst-case corners.
• A strong collaborator and communicator who can drive results across distributed, cross-functional engineering teams.

What We Need

• Drive timing convergence across blocks, partitions, sections, and top-level designs; generate and validate timing models and publish results.
• Analyze timing violations, develop and propagate fixes, debug timing-flow issues, and keep execution progressing through tapeout.
• Develop and validate bottom-up constraints while partnering with Design and DFT teams on methodology updates and closure requirements.
• Use Python, Perl, and Tcl for automation and flow development; experience with SPICE, PNR, placement, CTS, routing, post-route optimization, DFT, or AI-based automation is a plus.

What You Will Learn

• How to develop scalable timing models, constraints, and closure strategies across multiple levels of design hierarchy.
• How clocking, guardbanding, derates, uncertainties, CDC, RDC, and process corners influence timing convergence.
• How timing, physical design, Design, and DFT methodologies come together to deliver successful tapeouts.
• How to improve implementation and signoff workflows through scripting, automation, flow development, and emerging AI-enabled solutions.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

This position requires access to technology that requires a U.S. export license for persons whose most recent country of citizenship or permanent residence is a U.S. EAR Country Groups D:1, E1, or E2 country.

This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.