Senior STA Signoff Architect — Elevate Silicon, Equity

NVIDIA; Santa Clara (CA); On-site; USD 168,000 - 311,000; Full time

Job summary

NVIDIA in Santa Clara, CA, is seeking an innovative Senior STA Signoff Methodology Engineer to advance timing, power, and reliability across GPU/SoC platforms. You’ll run large-scale SPICE simulations, develop STA/PNR flows, and collaborate with design and timing teams to push silicon performance to new limits.

Applicants should have an MS in Electrical or Computer Engineering and 8+ years in ASIC timing, RC extraction, and EDA tools.

Qualifications

• MS in Electrical or Computer Engineering, or equivalent experience.
• Solid understanding of RC extraction, device physics, STA methodologies, and EDA-tool limitations.
• Hands-on experience with 5 nm, 3 nm, 2 nm FinFETs and beyond.

Responsibilities

• Run large-scale SPICE simulations and STA experiments to model timing impacts of advanced technologies.
• Develop STA and PNR flows addressing aging, self-heating, thermal effects, IR drop and other physical effects.
• Collaborate with technology leads, physical design and timing engineers to define timing-signoff strategies.
• Develop tools and methodologies to improve design performance and silicon reliability beyond standard EDA tools.
• Work across STA, constraints, and timing and power optimization.
• Perform extensive data analysis using Python, JMP, or similar tools to improve STA-to-silicon correlation.

Skills

ASIC timing analysis

Python scripting

Data analysis

Team collaboration

Education

MS in Electrical or Computer Engineering

Tools

PrimeTime

ICC2

RedHawk

Tempus

Job description

NVIDIA in Santa Clara, CA, is seeking an innovative Senior STA Signoff Methodology Engineer to advance timing, power, and reliability across GPU/SoC platforms. You’ll run large-scale SPICE simulations, develop STA/PNR flows, and collaborate with design and timing teams to push silicon performance to new limits.

Applicants should have an MS in Electrical or Computer Engineering and 8+ years in ASIC timing, RC extraction, and EDA tools.