Senior STA Lead for Cloud-Scale ML Hardware

Amazon Web Services (AWS); Cupertino (CA); On-site; USD 240,000 - 324,000; Full time

Benefits offered by this job

RSUs

Health insurance

401(k)

Job summary

Annapurna Labs (U.S.) Inc. in Cupertino, CA, seeks an experienced Sr. Physical Design STA Engineer to advance cloud server platforms with high-performance, low-cost hardware.

You will help design AI/ML acceleration hardware and work across RTL, architecture, and physical teams to optimize timing and power in large-scale data center chips. You will lead timing-constraint development, automate STA workflows, and provide ECO guidance while collaborating with multiple engineering disciplines to

Qualifications

• 7+ years of ASIC implementation, synthesis, STA and physical design in 16nm or smaller.
• 7+ years of digital design in communication systems experience.
• 7+ years of full-custom analog or RF layout experience.
• 7+ years of wireless communications systems and implementation experience.
• 8+ years of automation frameworks for Post-Silicon Flow experience.
• 3+ years of emulation experience.
• 3+ years doing Static Timing Analysis

Responsibilities

• Develop & maintain flows for block and full-chip level static timing analysis.
• Write, debug & validate timing constraints for blocks and full-chip.
• Run Static Timing Analysis and provide feedback to team members and leads.
• Provide guidance on fixing timing issues (ECOs, constraints).
• Develop scripts to automate timing analysis and reports.
• Collaborate with physical design and RTL/Arch teams to improve flows.

Skills

ASIC implementation

Synthesis

Static Timing Analysis

Physical design

UVM

Python

C

Timing analysis

Automation scripting

Education

BS + 8yrs in EE/CS

MS + 6yrs in EE/CS

PhD + 4yrs in EE/CS

Tools

PrimeTime

Tempus

Job description

Annapurna Labs (U.S.) Inc. in Cupertino, CA, seeks an experienced Sr. Physical Design STA Engineer to advance cloud server platforms with high-performance, low-cost hardware.

You will help design AI/ML acceleration hardware and work across RTL, architecture, and physical teams to optimize timing and power in large-scale data center chips. You will lead timing-constraint development, automate STA workflows, and provide ECO guidance while collaborating with multiple engineering disciplines to