Senior SRAM Engineer — AI Chips, Equity

NVIDIA; Santa Clara (CA); On-site; USD 196,000 - 311,000; Full time

Job summary

NVIDIA is seeking a Senior SRAM Engineer to design and optimize SRAM circuits for advanced AI chips. You will work with a team on cutting-edge memory technologies, collaborating with mask designers to deliver dense, high-performance layouts and reliable silicon.

You will apply rigorous verification, STA/EM/IR analyses, and develop flows to improve automation and data-driven decision making across the SRAM design flow.

Qualifications

• BS/MS/PhD in Electrical or Computer Engineering.
• Minimum 12 years of circuit design experience.
• Strong understanding of SRAM and memory design techniques and macro/block development.
• Familiarity with Cadence Virtuoso for schematic and layout, SPICE simulators, waveform viewers.
• Background with Static Timing Analysis, EM and IR analysis, Formal Functional Verification.
• Experience with scripting languages - Perl, Python, Shell, Verilog.

Responsibilities

• Design best-in-class SRAM circuits using state-of-the-art technology processes.
• Optimize circuits for performance, area, and power.
• Collaborate with mask designers to craft high quality and dense pitch-matched layout.
• Verify functionality, electrical integrity, and robustness.
• Improve/develop flows and methodologies to streamline design automation, data collection, and analysis to ensure working silicon.

Skills

SRAM circuit design

Memory design techniques

Cadence Virtuoso

Scripting (Perl, Python, Shell, Verlog

Static Timing Analysis

EM/IR analysis

Formal verification

Verilog

Education

BS/MS/PhD in Electrical or Computer Engineering

Tools

Cadence Virtuoso

SPICE simulators

Job description

NVIDIA is seeking a Senior SRAM Engineer to design and optimize SRAM circuits for advanced AI chips. You will work with a team on cutting-edge memory technologies, collaborating with mask designers to deliver dense, high-performance layouts and reliable silicon.

You will apply rigorous verification, STA/EM/IR analyses, and develop flows to improve automation and data-driven decision making across the SRAM design flow.