Senior SoC Verification Methodology Engineer

NVIDIA; United States; On-site; USD 168,000 - 310,500; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA is seeking a Senior Verification Infrastructure Engineer to enhance its verification processes. This role involves building and maintaining verification infrastructure for System level simulations and FPGA prototyping, ensuring performance and quality across NVIDIA’s SoCs.

Candidates should possess a Master's degree in Electrical Engineering and over 8 years of experience in verification methodologies including SystemVerilog and UVM. NVIDIA offers a competitive salary of 168,000 - 264,500 USD for Level 4, and 196,000 - 310,500 USD for Level 5, along with equity and benefits.

Qualifications

• 8+ years of experience in modern verification methodologies.
• Hands-on experience with hardware emulation, FPGA prototyping, or C-model verification.
• Strong debugging skills across hardware and software boundaries.

Responsibilities

• Build and develop testbench infrastructure for verification of NVIDIA SoCs.
• Develop and support reusable verification components.
• Collaborate closely with design and architecture teams.

Skills

SystemVerilog

UVM

Verification IP (VIP)

RTL simulation

Scripting in Python or Perl

Education

Master’s Degree in Electrical Engineering or equivalent

Job description

We are looking for a Senior Verification Infrastructure Engineer to join the SoC verification team at NVIDIA. In this role, you will build, develop, and maintain scalable verification infrastructure that enables efficient system-level verification across System level Simulations, Emulation, FPGA prototyping, and C-model environments. Your work will be foundational to ensuring correctness, performance, and quality of NVIDIA’s SoCs used across AI Datacenters, self-driving cars, robotics, and embedded platforms. This is your chance to work with innovative technology and make a significant impact on the future of computing!

What You’ll Be Doing

• Build and develop testbench infrastructure and associated flows for full chip level verification of NVIDIA SoCs
• Develop, combine, and support Verification IP (VIP) and reusable verification components
• Develop and improve stimulus frameworks supporting: RTL simulation, Hardware emulation, FPGA prototyping, C-model and hybrid model verification.
• Work closely with EDA vendors to co-develop and deploy new verification tooling.
• Collaborate closely with design, architecture, performance, and software teams to align verification infrastructure with evolving product requirements
• Drive best practices in verification methodology, scalability, performance optimization, and debuggability
• Support bring-up and debug of system-level test environments and flows

What We Need To See

• Master’s Degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent experience
• 8+ years in the following areas: SystemVerilog, UVM, and modern verification methodologies
• Experience working with testbenches, VIP, and reusable verification frameworks
• Hands‑on experience with RTL simulation and at least one of the following: Hardware emulation, FPGA prototyping, C-model or virtual platform verification.
• Solid scripting skills in Python or Perl, or similar for automation and tooling
• Strong debugging skills across hardware and software boundaries

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 168,000 USD - 264,500 USD for Level 4, and 196,000 USD - 310,500 USD for Level 5.

You will also be eligible for equity and benefits.

Applications for this job will be accepted at least until January 24, 2026.

This posting is for an existing vacancy.

NVIDIA uses AI tools in its recruiting processes.

NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.