Senior STA Engineer - HBM Timing & AI-Driven Closure

1000 Micron Technology, Inc.; Folsom (CA); On-site; USD 199,000 - 347,000; Full time

Benefits offered by this job

Medical, dental and vision plans

Paid family leave

Robust paid time-off program

Paid holidays

Job summary

Micron Technology, Inc. is seeking an experienced Static Timing Analysis (STA) Engineer to own chip-level timing sign-off for next-generation HBM products and to collaborate across RTL, physical design, DFT, verification, and product teams.

You will apply AI-driven tools and workflows to timing methodologies, develop sign-off standards, and drive timing closure from design through tape-out, including post-silicon correlation and automation via Python and Tcl.

Qualifications

• 15+ years of hands-on experience owning chip-level static timing analysis and full timing sign-off on multiple tape-outs at 5nm or below.
• Deep expertise with Synopsys PrimeTime and/or Cadence Tempus for STA sign-off.
• Proven ability to develop and manage complex hierarchical SDC constraints for large SoCs with multiple clock and power domains.
• Proficiency in Python and/or Tcl scripting for timing flow automation, constraint management, and reporting.

Responsibilities

• Own end-to-end chip-level static timing analysis and sign-off across all checks, modes, corners, and voltage/temperature conditions.
• Drive timing closure at block, subsystem, and full-chip levels with ECOs and collaboration with physical design.
• Develop, maintain, and validate SDCs for clocks, resets, and high-bandwidth memory interfaces.
• Lead MMMC analysis including clock domain crossing timing and on-chip variation.

Skills

Timing closure ownership

Python scripting

Tcl scripting

Synopsys PrimeTime

Cadence Tempus

Tools

Primetime

Tempus

Job description

Micron Technology, Inc. is seeking an experienced Static Timing Analysis (STA) Engineer to own chip-level timing sign-off for next-generation HBM products and to collaborate across RTL, physical design, DFT, verification, and product teams.

You will apply AI-driven tools and workflows to timing methodologies, develop sign-off standards, and drive timing closure from design through tape-out, including post-silicon correlation and automation via Python and Tcl.