Senior STA Engineer – HBM & AI‑Driven Timing Sign‑Off

Micron Technology, Inc; Folsom (CA); On-site; USD 199,000 - 347,000; Full time

Job summary

Micron Technology, Inc. is seeking a senior SoC Static Timing Analysis Engineer for HBM products. The role owns chip‑level timing sign‑off across modes and corners, driving AI‑assisted timing methodologies and sign‑off readiness from design through tape‑out.

You will collaborate with RTL, physical design, DFT, and verification teams to ensure timing integrity, build automation, and enable AI‑driven workflows for improved efficiency.

Qualifications

• Owning chip-level STA and timing sign-off on multiple tape-outs (5nm or below).
• Expert with prime timing tools and cadence flows for timing analysis and sign-off.
• Strong Python/Tcl for timing flow automation and reporting.

Responsibilities

• Drive development of AI‑enabled timing closure methods for next‑gen chips.
• Own end-to-end chip-level STA sign-off across all checks, modes, corners, and conditions.
• Develop, validate, and maintain SDC constraints for clocks, resets, and interfaces.
• Collaborate with RTL, physical design, and DFT teams to achieve timing closure.
• Perform MMMC analysis including clock domain crossing and OCV variants.
• Lead automation for timing flows and post‑silicon timing correlation.

Skills

Python scripting

Tcl scripting

Timing closure

SDC constraints

Tools

Synopsys PrimeTime

Cadence Tempus

Job description

Micron Technology, Inc. is seeking a senior SoC Static Timing Analysis Engineer for HBM products. The role owns chip‑level timing sign‑off across modes and corners, driving AI‑assisted timing methodologies and sign‑off readiness from design through tape‑out.

You will collaborate with RTL, physical design, DFT, and verification teams to ensure timing integrity, build automation, and enable AI‑driven workflows for improved efficiency.