Senior SoC RTL Design Engineer (remote)

California Jobs; Los Angeles (CA); Remote; USD 120,000 - 160,000; Full time

Job summary

A leading company in the semiconductor sector seeks a Senior RTL Design Engineer to work remotely from any US location. The role encompasses designing complex SoC blocks, performing silicon bring-up, and collaborating on architectural feasibility studies. Candidates must possess a BSEE/MSEE and extensive experience in SoC design, with a competitive salary package including bonuses and stock options.

Benefits

Bonus

Benefits package

401k

Stock Options

Qualifications

• 10+ years of SoC design/architecture experience required.
• Experience with standard bus protocols like AXI/AMBA/TileLink is a plus.
• Working knowledge of PCIe and DDR required.

Responsibilities

• Assist with silicon bring-up and design complex SoC blocks.
• Develop micro-architecture specifications based on the SoC requirements.
• Identify and resolve RTL and GLS failures at block and chip level.

Skills

Asynchronous logic design

Clock domain crossing methodologies

RISC-V architecture

Logic synthesis

Static timing analysis

Modeling SoC architectures

RTL Design

Scripting languages (Python, Perl, Tcl)

EDA tools

Problem solving and debugging

Education

BSEE/MSEE

Job description

Senior RTL Design Engineer
Remote / work from any US location
US Citizen or US Permanent Resident
Full-time/employee + Bonus, Benefits, 401k, Stock Options, etc

Responsibilities:
• Assist with silicon bring-up
• Design, implement and integrate complex SoC blocks
• Develop block-level test cases to deliver fully functional designs
• Develop micro-architecture specifications based on the SoC requirements
• Develop synthesis constraints and resolve timing issues
• Identify and resolve RTL and GLS failures at block and chip level
• Participate in architectural feasibility studies
• Participate in ECO implementation
• Resolve Lint, CDC, and DFT related issues

Required Skills & Experience:
• BSEE/MSEE with 10+ years of SoC design/architecture experience
• Asynchronous logic design is a plus
• Clock domain crossing methodologies
• Experience with RISC-V architecture
• Logic synthesis and static timing analysis
• Modeling SoC architectures with FPGAs
• RTL Design including HVLs and HDLs (SystemVerilog, Verilog)
• Scripting languages such as Python, Perl, Tcl, shell, etc.
• SoC design flow including chip-level design, block/IP design and behavioral modeling
• Strong familiarity with EDA tools
• Strong problem solving and debugging capabilities
• Third Party IP Integration experience
• Working knowledge of PCIe and DDR
• Working knowledge of SoC design with CHISEL is a plus
• Working knowledge of standard bus protocols such as AXI/AMBA/TileLink

About the company

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