Senior SoC Power Engineer for AI Accelerators

Amazon; Cupertino (CA); On-site; USD 183,000 - 248,000; Full time

Benefits offered by this job

Health benefits

Job summary

Amazon is seeking a Sr. SoC Power Engineer for the MLA team in Cupertino to model and estimate power from RTL to final netlist and drive approaches to reduce power in Inferentia and Trainium accelerators.

You will work with architects, designers, verification, software, and Physical Design to develop power analysis methods, create dashboards, and provide actionable feedback to RTL and physical designers.

Qualifications

• Bachelor's degree in Computer Science, Computer Engineering, Electrical Engineering, or related fields.
• BS + 6yrs or MS + 5yrs or PhD + 3yr in EE/CS.
• Expert on power analysis tools like PrimePower, PowerArtist or similar.
• Deep, circuit-level understanding of chip power.
• Ability to give feedback to RTL designers and Physical Designers on how to reduce power.
• Highly proficient with scripting language (Tcl, Perl, Python or similar).
• Good understanding of Physical Design, EM/IR, Power Integrity, and Thermal at the die, package, board, and server level.
• Some experience with lab equipment and capable of doing lab power analysis.

Responsibilities

• Responsible for full chip power analysis & modelling at various stages of design (RTL to gate level netlist).
• Develop and maintain dashboards for power rollups.
• Work with designers, architects, Verification engineers and Physical Design engineers to develop vectors for IR analysis, Thermal analysis and power estimation.
• Give feedback to designers and architects on how to reduce power.
• Make power measurements in the lab and correlate back to simulations.
• Work with Emulation engineers to model chip-level power consumption.

Skills

Power analysis

Scripting (Tcl/Python)

Power integrity

Lab power analysis

Education

Bachelor's degree in EE/CS

Master's degree

PhD

Tools

PrimePower

PowerArtist

Redhawk/Voltus

Job description

Amazon is seeking a Sr. SoC Power Engineer for the MLA team in Cupertino to model and estimate power from RTL to final netlist and drive approaches to reduce power in Inferentia and Trainium accelerators.

You will work with architects, designers, verification, software, and Physical Design to develop power analysis methods, create dashboards, and provide actionable feedback to RTL and physical designers.