Senior SOC Design & Methodology Engineer (Equity)

NVIDIA; Santa Clara (CA); On-site; USD 168,000 - 265,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA is seeking a Senior CPU Design Methodology Engineer to advance SOC design methodologies and automation across front-end and RTL flows. You will collaborate with ASIC, Physical Design, CAD, Package Design, Software, and DFT teams to build complex CPUs.

The role emphasizes developing scalable methodologies, optimizing front-end processes, and delivering high-quality RTL for integration with the chip assembly flow. Excellent analytical and coding skills are essential for success.

Qualifications

• Masters in Computer or Electrical Engineering required.
• 8+ years of chip design experience, SOC integration and design automation.
• Excellent analytical and problem-solving skills.
• Experience in RTL design (Verilog), verification (UVM, SystemVerilog), SOC design/integration flow, and design automation.
• Strong coding skills in Perl, Python, or other industry-standard scripting languages.
• Experience in synthesis and physical design is a plus.
• Good interpersonal skills.

Responsibilities

• Define and develop system-level methodologies and tools to build SOCs efficiently and at scale.
• Identify inefficiencies in front-end chip implementation and propose improvements.
• Own front-end design quality checks and reviews to deliver high-quality RTL to the physical design team.

Skills

RTL design (Verilog)

Verification (UVM,SystemVerilog)

SoC design/integration flow

Design automation

Perl/Python scripting

Analytical skills

Interpersonal skills

Education

Masters in Computer or Electrical Engineering

Tools

Synthesis

Physical design

Job description

NVIDIA is seeking a Senior CPU Design Methodology Engineer to advance SOC design methodologies and automation across front-end and RTL flows. You will collaborate with ASIC, Physical Design, CAD, Package Design, Software, and DFT teams to build complex CPUs.

The role emphasizes developing scalable methodologies, optimizing front-end processes, and delivering high-quality RTL for integration with the chip assembly flow. Excellent analytical and coding skills are essential for success.