Senior Silicon Photonics PIC Design Engineer

Advanced Micro Devices, Inc.

San Jose (CA)

Vor Ort

USD 180.000 - 280.000

Vollzeit

Vor 5 Tagen
Sei unter den ersten Bewerbenden

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Benefits dieser Stelle

AMD benefits at a glance

Zusammenfassung

Advanced Micro Devices, Inc. in San Jose is seeking a seasoned technical contributor to drive end-to-end delivery of PIC solutions for optical IO used in next-generation AI and HPC applications.

You will coordinate with hardware engineering teams and AMD partners to plan, develop, and optimize PIC solutions, focusing on DFx, test methodologies, and high-volume manufacturing readiness.

Qualifikationen

  • Masters or PhD degree in Applied Physics/Electrical Engineering or related discipline.
  • Significant success in driving photonic PDK, device and circuit design.
  • Experience with photonic design automation, DFx, and software for analysis with Python.

Aufgaben

  • Develop OE systems in advanced Si photonics for DWDM/CWDM in AI/HPC apps.
  • Define and specify PIC architectures, TX/RX chains and test methodologies.
  • Maintain and optimize Optical IO link budgets across product requirements and foundry capabilities.
  • Design-for-test best practices to enable high-volume manufacturing.
  • Participate in design reviews as a subject matter expert in silicon photonic component design.
  • Collaborate with EIC, packaging, foundry technology, test development, and product teams on design/test automation.

Kenntnisse

PIC theory
Device design
Circuit layout
Photonic design automation
Test automation
Data analysis
Python

Ausbildung

Masters or PhD in Applied Physics/Electrical Engineering or related discipline

Tools

Cadence
FDTD
MODE

Jobbeschreibung

Advanced Micro Devices, Inc. in San Jose is seeking a seasoned technical contributor to drive end-to-end delivery of PIC solutions for optical IO used in next-generation AI and HPC applications.

You will coordinate with hardware engineering teams and AMD partners to plan, develop, and optimize PIC solutions, focusing on DFx, test methodologies, and high-volume manufacturing readiness.

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