Senior Signal Integrity Engineer (High-Speed SerDes)

Socket.dev; Wayne (CA); On-site; USD 144,000 - 230,000; Full time

Benefits offered by this job

Medical, dental and vision plans

401(K) with company match

Employee Stock Purchase Program (ESPP)

Employee Assistance Program (EAP)

Paid holidays, sick leave and vacation

Job summary

Broadcom is seeking a Senior SI/PI Engineer to own signal and power integrity analysis for high‑speed boards, packages, and system architectures. You will work with hardware, ASIC, SERDES, packaging, and layout teams from architecture trade‑offs to lab bring‑up and characterization.

You will build accurate 2.5D/3D EM models, perform time- and frequency-domain simulations, and validate designs in the lab while driving design rules and automation through scripting.

Qualifications

• BS/MS/PhD in Electrical Engineering, Computer Engineering, or related field.
• 12+ years of high-speed digital design, SI, and PI experience.
• Strong fundamentals in transmission line theory, S-parameters, crosstalk, jitter, EMI/EMC, and PDN concepts.
• Proven ability to model with 2.5D/3D EM tools and verify with lab measurements.

Responsibilities

• Model 2.5D/3D EM models for high-speed channels, substrates, connectors, and PCB stackups.
• Run time- and frequency-domain simulations for SerDes and high-speed interfaces.
• Lead PDN analysis for impedance targets, transient noise, and IR drop.
• Provide layout constraints, stackup guidance, and routing rules.
• Validate simulations in lab using VNAs, TDRs, and oscilloscopes; correlate data to models.
• Debug SI/PI issues during board bring-up and drive root-cause analyses.
• Develop scripts (Python/TCL) to automate flows and data processing.

Skills

Signal Integrity

Power Integrity

EM Modeling

Lab Equipment

Education

BS/MS/PhD in Electrical Engineering or related field

Tools

HFSS/SiWave

Sigrity/Allegro

Keysight ADS

HSPICE

Job description

Broadcom is seeking a Senior SI/PI Engineer to own signal and power integrity analysis for high‑speed boards, packages, and system architectures. You will work with hardware, ASIC, SERDES, packaging, and layout teams from architecture trade‑offs to lab bring‑up and characterization.

You will build accurate 2.5D/3D EM models, perform time- and frequency-domain simulations, and validate designs in the lab while driving design rules and automation through scripting.