Principal Engineer, System HW Design - SI/PI

DeWinter BH; San Jose (CA); On-site; USD 210,000 - 280,000; Full time

Job summary

DeWinter Group seeks a Principal Engineer, System HW Design – SI/PI to lead the corporate SI/PI strategy for advanced ML hardware platforms. You will guide PCB designs spanning SoMs, PCIe cards, and chip-down references, and drive lab validation to production readiness.

You will work across ASIC, package, hardware, firmware, and manufacturing teams to close high-speed margins and ensure robust power delivery.

Qualifications

• Bachelor’s degree in Electrical Engineering or related field required.
• Approximately 15 years of industry experience in SI/PI for high-speed digital systems.
• Experience leading SI/PI strategy across multiple hardware programs.
• Proficiency with PCIe Gen4/Gen5 up to 32 GT/s, DDR4/DDR5/LPDDR, USB 3.x, USB-C, MIPI D-PHY/C-PHY, 10 GbE SerDes.
• Knowledge of PCB stack-up design, impedance control, and S-parameters.
• Experience with SI/PI tools and lab validation.

Responsibilities

• Lead SI/PI strategy and standards across programs.
• Design, build, bring up, characterize, and productize PCB systems (SoMs, PCIe cards, reference designs).
• Mentor senior engineers and collaborate across ASIC, package, hardware, firmware, and manufacturing teams.
• Drive margin closure on high-speed interfaces and power delivery for compute silicon.
• Develop reusable simulation methodologies and validation flows.

Skills

SI/PI leadership

PCIe Gen4/Gen5 up to 32 GT/s

DDR4/DDR5/LPDDR channels

MIPI D-PHY/C-PHY

USB 3.x / USB-C

SerDes high-speed interfaces

lab validation with VNAs/TDRs/oscillsc

SI/PI EDA tools (HFSS/SIwave, Sigrity/

Education

Bachelor’s degree in Electrical Engineering

Master’s degree in Electrical Engineering

Tools

Ansys HFSS

Siwave

Cadence Sigrity/Clarity

Keysight ADS

Job description

Principal Engineer, System HW Design – Signal Integrity / Power Integrity (SI/PI)

Overview

Lead the signal integrity and power integrity strategy for a portfolio of advanced machine-learning hardware platforms. As Principal Engineer, System HW Design – SI/PI, you will help design, build, bring up, characterize, and productize PCB systems spanning System-on-Module designs, PCIe add-in cards, chip-down BGA reference designs, development kits, and future platforms.

This is a high-impact technical leadership role for an engineer who can establish organization-wide SI/PI standards, guide complex board designs, close high-speed interface margins, and solve the most challenging lab validation and bring-up issues. You will work across ASIC, package, hardware, layout, firmware, manufacturing, and external vendor teams to deliver reliable high-speed signaling and power delivery for advanced compute systems.

Required Skills and Qualifications

• Bachelor’s degree in Electrical Engineering or a related field.
• Approximately 15 years of industry experience in signal integrity and power integrity engineering for high-speed digital systems.
• Experience leading SI/PI strategy across multiple concurrent hardware programs.
• Deep expertise with:
• PCIe Gen4/Gen5, including PCIe Gen5 operation up to 32 GT/s per lane.
• DDR4, DDR5, and LPDDR memory channels.
• USB 3.x and USB Type-C.
• MIPI D-PHY and C-PHY.
• 10 Gigabit Ethernet SerDes.
• Proven experience driving high-speed interface margin closure on production designs.
• Track record owning power delivery network architecture for high-power SoCs, ASICs, AI accelerators, GPUs, or comparable compute silicon.
• Expert proficiency with SI/PI EDA tools such as Ansys HFSS/SIwave, Cadence Sigrity/Clarity, Keysight ADS, or equivalent platforms.
• Experience selecting SI/PI tools and developing reusable simulation methodologies.
• Extensive hands-on lab validation experience using VNAs, TDRs, and high-bandwidth oscilloscopes.
• Experience owning escalation-level SI/PI debug.
• Expertise in PCB stack-up design, impedance control, transmission line theory, S-parameters, and channel modeling.
• Strong working knowledge of PCIe-SIG, USB-IF, and MIPI Alliance compliance standards.
• Ability to define technical direction, establish engineering standards, and mentor senior- and staff-level engineers.
• Strong cross-functional leadership skills, with the ability to align ASIC, package, hardware, layout, and firmware teams.
• Proactive, solutions-oriented approach with a strong sense of ownership and accountability.
• Excellent verbal and written communication skills, including the ability to explain complex technical concepts to diverse audiences.

Nice-to-Have Skills

• Master’s degree in Electrical Engineering or a related field.
• Knowledge of ASIC characterization, PCB manufacturing, assembly, test, quality, and reliability.
• Experience supporting or owning PCIe-SIG, USB-IF, or MIPI Alliance compliance testing.
• Experience defining connector and interconnect strategies across multiple product generations.
• Experience working with board-to-board, M.2 NVMe, and PCIe edge-card interfaces.
• Experience engaging with component and module vendors or industry standards organizations.
• A record of delivering complex technical programs in ambiguous, fast-moving environments.
• Creative and intellectually curious approach to solving challenging hardware problems.

Preferred Education and Experience

• Bachelor’s degree in Electrical Engineering or a related discipline required.
• Master’s degree preferred.
• Approximately 15 years of professional experience in SI/PI engineering for high-speed digital systems preferred.
• Demonstrated experience providing product-line-level technical leadership across multiple board programs.

Other Requirements

• Work arrangement: Fully onsite in San Jose.
• Contract assignment initially expected to run for six months, with potential for extension.
• Ability to work collaboratively across internal engineering teams and external vendors.
• Ability to drive long-term SI/PI architecture, methodology, and standards while remaining hands-on with design, simulation, validation, and debug.