Senior SI/PI Engineer - Satellite Payloads

SPACE EXPLORATION TECHNOLOGIES CORP; Palo Alto (CA); On-site; USD 180,000 - 250,000; Full time

Job summary

SPACE EXPLORATION TECHNOLOGIES CORP is seeking a Signal and Power Integrity Engineer for the Starlink payload team in Palo Alto. You will own SI/PI across the hardware life cycle, interfacing with RF, ASIC, packaging, thermal, software, and antenna engineers to drive robust designs.

You will evaluate silicon architecture, guide PDN and channel design, and oversee PCB layout and verification workflows. A strong background in 3D EM tools, high‑speed digital interfaces, and power integrity is

Qualifications

• Bachelor’s degree in electrical engineering, computer engineering, or physics.
• 5+ years designing circuits, electronic products, or hardware.
• 2+ years using 3D EM simulation tools (CST, HFSS, ADS).
• 2+ years of research or industry experience with high‑speed digital design or power integrity.

Responsibilities

• Specify, design, simulate, verify, qualify SI/PI for advanced satellite hardware.
• Collaborate with RF, antenna, ASIC, packaging, thermal, software, and production teams.
• Derive specifications for PCB materials and channel subcomponents.
• Drive PDN design, transitions, and component selection.
• Root cause and fix issues in PCB manufacturing and satellite integration.
• Define best practices and lab equipment needs for SI/PI across Starlink payloads.

Skills

Python

C/C++

EM theory

Power integrity

DSP SERDES

PCB design

Cross-functional teamwork

Education

Bachelor’s degree in electrical engineering, computer engineering, or physics

Master’s degree or PhD in electrical engineering or related field

Tools

HFSS

CST

ADS

Job description

SPACE EXPLORATION TECHNOLOGIES CORP is seeking a Signal and Power Integrity Engineer for the Starlink payload team in Palo Alto. You will own SI/PI across the hardware life cycle, interfacing with RF, ASIC, packaging, thermal, software, and antenna engineers to drive robust designs.

You will evaluate silicon architecture, guide PDN and channel design, and oversee PCB layout and verification workflows. A strong background in 3D EM tools, high‑speed digital interfaces, and power integrity is