Senior Security IP Verification Engineer

Arm; Austin (TX); Hybrid; USD 162,000 - 219,000; Full time

Benefits offered by this job

Hybrid work model

Accommodations on request

Job summary

Arm seeks creative Design Verification Engineers to join our Security IP team, focused on Cryptography, Key Management, and Hardware Root of Trust. You'll contribute to test planning, testbench development, and productization for pioneering SoC designs.

Responsibilities include developing test plans, UVM/SystemVerilog/Verilog testbenches, and debugging test failures, while mentoring others and aligning with design teams for sign‑off, power, and performance optimization.

Qualifications

• Bachelors or Masters in CS or ECE or similar field.
• 5+ years in design or verification of IP/SoCs or embedded subsystems.
• Experience with Verilog/SystemVerilog/UVM and testbench development.
• Experience with security IP verification, cryptography, and secure boot is a plus.
• Strong debugging, problem solving and collaboration skills.

Responsibilities

• Develop test plans, testbenches, verification models and strategies.
• Create and debug UVM/SystemVerilog/Verilog testbenches.
• Collaborate with design teams for sign‑off, coverage, power and performance.
• Mentor team members and contribute to verification methodologies.
• Balance project management initiatives and schedules.

Skills

Verilog HDL

SystemVerilog UVM

C

Formal verification

Hardware/Firmware co-verification

Perl

Python

Tcl

ARM-based designs

Embedded processors

AXI/AHB protocols

Education

Bachelor's or Master’s degree in Computer Science or Electrical/Computer Engineering

Tools

Perl

Python

Tcl

Job description

Arm seeks creative Design Verification Engineers to join our Security IP team, focused on Cryptography, Key Management, and Hardware Root of Trust. You'll contribute to test planning, testbench development, and productization for pioneering SoC designs.

Responsibilities include developing test plans, UVM/SystemVerilog/Verilog testbenches, and debugging test failures, while mentoring others and aligning with design teams for sign‑off, power, and performance optimization.