Senior RTL Networking ASIC Architect for AI Data Centers

Eridu Corp.; Saratoga, Northern (CA, KY); Hybrid; USD 210,000 - 275,000; Full time

Job summary

Eridu is a Silicon Valley-based hardware startup accelerating AI data centers with industry-leading Networking ASICs. We seek experienced RTL designers to define, specify, architect, execute, and productize advanced networking chips for improved AI performance.

You will join the Design Group to work on packet buffering, latency optimization, QoS support, and protocol interoperability, collaborating with system architects, hardware, and firmware engineers.

Qualifications

• ME/BE with 8–15 years of hardware design experience.
• Hands-on SystemVerilog and Verilog required.
• Experience designing scheduling and QoS in networking ASICs.

Responsibilities

• Packet buffering, queuing, and scheduling: design high-speed networking ASICs with latency and QoS focus.
• Implementation and Testing: implement designs on ASIC platforms with verification collaboration.
• Performance Optimization: optimize pipelining to improve metrics.
• Protocol Support: support Ethernet and IP protocols, and high-speed interconnects like UCIe.
• Troubleshooting and Debugging: resolve complex networking issues with cross-functional teams.

Skills

SystemVerilog

Verilog

ASIC design

Networking protocols

Education

ME/BE

Job description

Eridu is a Silicon Valley-based hardware startup accelerating AI data centers with industry-leading Networking ASICs. We seek experienced RTL designers to define, specify, architect, execute, and productize advanced networking chips for improved AI performance.

You will join the Design Group to work on packet buffering, latency optimization, QoS support, and protocol interoperability, collaborating with system architects, hardware, and firmware engineers.