RTL Engineer, Networking ASIC

Eridu Corp.; Saratoga (CA); Hybrid; USD 210,000 - 275,000; Full time

Job summary

Eridu is a Silicon Valley-based hardware startup accelerating AI data centers with industry-leading Networking ASICs. We seek experienced RTL designers to define, specify, architect, execute, and productize advanced networking chips for improved AI performance.

You will join the Design Group to work on packet buffering, latency optimization, QoS support, and protocol interoperability, collaborating with system architects, hardware, and firmware engineers.

Qualifications

• ME/BE with 8–15 years of hardware design experience.
• Hands-on SystemVerilog and Verilog required.
• Experience designing scheduling and QoS in networking ASICs.

Responsibilities

• Packet buffering, queuing, and scheduling: design high-speed networking ASICs with latency and QoS focus.
• Implementation and Testing: implement designs on ASIC platforms with verification collaboration.
• Performance Optimization: optimize pipelining to improve metrics.
• Protocol Support: support Ethernet and IP protocols, and high-speed interconnects like UCIe.
• Troubleshooting and Debugging: resolve complex networking issues with cross-functional teams.

Skills

SystemVerilog

Verilog

ASIC design

Networking protocols

Education

ME/BE

Job description

Eridu is a Silicon Valley-based hardware startup pioneering infrastructure solutions that accelerate AI data centers to deliver Faster AI . Today’s AI performance is frequently limited by communication bottlenecks. Eridu introduces multiple industry-first innovations across silicon, packaging, software, and systems to deliver an order of magnitude improvement in performance and unlock greater GPU utilization to speed training job completion times and tokens-per-second for more profitable inference. We do this while simultaneously reducing capital and power costs and improving reliability.

The company’s solutions and value proposition have been widely validated by leading hyperscalers.

Eridu has raised over $200M to date including its most recent, oversubscribed Series A round. The company is led by a veteran team of Silicon Valley executives who have delivered multiple billion dollar product lines and led multiple companies to billion dollar exits, including serial entrepreneur Drew Perkins, co-founder of Infinera (NASDAQ: INFN), Lightera (acq. by Ciena), Gainspeed (acq. by Nokia) and Mojo Vision (the world’s leading micro-LED company). The company is in execution mode and has a world-class engineering team with decades of experience in state-of-the-art silicon, packaging, optics, software, and systems. Eridu is working with best-in-class supply chain partners including silicon, packaging and systems.

Visit our website eridu.ai to learn more.

Position Overview

We are seeking experienced RTL designers to help define and implement our industry-leading Networking ASIC’s. If you're a highly motivated self-starter eager to solve real-world problems, this is a unique opportunity to shape the future of AI Networking. As part of the Design Group, you will be responsible for defining, specifying, architecting, executing, and productizing cutting-edge Networking chips.

Responsibilities

• Packet buffering, queuing, and scheduling: Work on micro architecture and design implementation of high-speed networking ASIC’s, focusing on latency optimization and quality of service (QoS) support. Prior experience with on-chip memory subsystem and scheduling / arbitration design.
• Implementation and Testing: Implement designs on ASIC platforms, ensuring compliance with industry standards and performance benchmarks. Work with verification team to conduct thorough testing and validation to ensure functionality and reliability.
• Performance Optimization: Analyze and optimize pipelining architectures to improve performance metrics.
• Protocol Support: Provide support for various networking protocols such as Ethernet and IP protocols, and high speed interconnects such as UCIe.
• Troubleshooting and Debugging: Investigate and resolve complex issues related to packet queuing, working closely with cross-functional teams, including system architects, hardware engineers, and firmware developers.

Qualifications

• ME/BE with a minimum of 8-15 years of experience.
• Hands-on knowledge of SystemVerilog and Verilog is mandatory .
• Solid understanding of ASIC design methodologies, including simulation, verification, synthesis, and timing adjustments.
• Proven expertise in designing and optimizing scheduling and QoS mechanisms.
• Experience with Ethernet and IP protocols.
• Strong analytical and problem-solving abilities, with meticulous attention to detail in troubleshooting and debugging complex networking issues.
• Excellent verbal and written communication skills, with the ability to collaborate effectively in a team environment and present technical information to diverse audiences.

Why Join Us?

At Eridu, you’ll have the opportunity to shape the future of AI infrastructure, working with a world-class team on groundbreaking technology that pushes the boundaries of AI performance. Your contributions will directly impact the next generation of AI infrastructure solutions, transforming the performance of AI data centers.

The starting base salary for the selected candidate will be established based on their relevant skills, experience, qualifications, work location, market trends, and the compensation of employees in comparable roles.

Notice to Recruiting Agencies

Eridu does not accept unsolicited resumes or candidate profiles from staffing agencies or third-party recruiters. Any candidate submitted to Eridu without prior written authorization from our recruiting team will be considered unsolicited and will become the property of Eridu. Eridu reserves the right to pursue and hire such candidates without any obligation to pay fees. Recruiting agencies are expressly instructed not to contact hiring managers, employees, or executives regarding open positions.

The pay range for this role is:

210,000 - 275,000 USD per year (San Francisco Bay Area)