Senior RTL Design Engineer (remote)

Chelsea Search Group, Inc.; San Diego (CA); Remote; USD 90,000 - 150,000; Full time

Job summary

An innovative firm is seeking a Senior RTL Design Engineer to join a talented team of SoC Engineers. In this exciting role, you will contribute to the design, verification, and implementation of cutting-edge methodologies and architectures. Your expertise will drive projects that range from integrating third-party IPs to designing complex systems. If you are passionate about SoC design and eager to tackle challenges in a collaborative environment, this opportunity is perfect for you.

Benefits

Benefits

401k

Stock Options

Qualifications

• 7+ years of experience in RTL Design with HVLs and HDLs.
• Strong familiarity with EDA tools and problem-solving skills.

Responsibilities

• Participate in architectural feasibility studies and develop micro-architecture specifications.
• Design, implement, and integrate complex SoC blocks.

Skills

RTL Design

SystemVerilog

Verilog

Logic synthesis

Static timing analysis

SoC design flow

FPGA modeling

AXI/AMBA/TileLink protocols

RISC-V architecture

Python

Perl

Tcl

Shell scripting

EDA tools

Problem solving

Education

Bachelor’s degree in Electrical Engineering

Bachelor’s degree in Computer Engineering

Tools

EDA tools

Job description

Senior RTL Design Engineer
Remote / work from home
US Citizen or US Permanent Resident
Full-time/employee + Benefits + 401k + Stock Options

Summary

As Senior RTL Design Engineer, you will work in a small talented team of SoC Engineers researching, designing, and implementing novel methodologies and architectures. You will have the opportunity to contribute to all areas of SoC design, verification, and implementation. Projects range from integrating third party IPs to designing complex systems.

Responsibilities:

1. Participate in architectural feasibility studies
2. Develop micro-architecture specifications based on the SoC requirements
3. Design, implement and integrate complex SoC blocks
4. Develop block-level test cases to deliver fully functional designs
5. Develop synthesis constraints and resolve timing issues
6. Resolve Lint, CDC, and DFT related issues
7. Identify and resolve RTL and GLS failures at block and chip level
8. Participate in ECO implementation
9. Assist with silicon bring-up

Required Skills / Experience:

1. Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field
2. 7+ years of RTL Design, including HVLs and HDLs (SystemVerilog, Verilog), and third-party IP integration experience
3. Logic synthesis and static timing analysis
4. SoC design flow including chip-level design, block/IP design and behavioral modeling
5. Modeling SoC architectures with FPGAs
6. Working knowledge of standard bus protocols such as AXI/AMBA/TileLink
7. Experience with RISC-V architecture
8. Working knowledge of PCIe and DDR
9. Clock domain crossing methodologies
10. Scripting languages such as Python, Perl, Tcl, shell, etc.
11. Strong familiarity with EDA tools
12. Strong problem solving and debugging capabilities
13. Working knowledge of SoC design with CHISEL is a plus
14. Asynchronous logic design is a plus