Senior RTL Design Engineer

Oho Group; San Francisco (CA); On-site; USD 140,000 - 210,000; Full time

Job summary

Oho Group is seeking an RTL Design Engineer to join a high-growth AI hardware startup in San Francisco. You will design and implement RTL for advanced digital and SoC designs, and translate architecture into efficient hardware solutions.

You will optimise for performance, power and area, work with verification and implementation teams, debug issues, and contribute to technical reviews and silicon bring-up. Experience in ASIC/SoC, AMBA, and memory systems is required.

Qualifications

• Strong ASIC and SoC design experience.
• Deep understanding of AMBA protocols.
• Knowledge of high-bandwidth memory systems (HBM, DDR).
• Experience designing high-performance compute engines in GPU or NPU.
• Familiarity with chiplet architectures or advanced packaging.
• Experience with performance modeling and architecture exploration.

Responsibilities

• Design and implement RTL for advanced digital and SoC designs.
• Translate architectural requirements into efficient hardware solutions.
• Optimise designs for performance, power, and area.
• Work with verification and implementation teams to deliver high-quality silicon.
• Debug and resolve design issues throughout development and silicon bring-up.
• Contribute to technical reviews and cross-functional engineering discussions.

Skills

ASIC design

SoC design

AMBA protocols

HBM / DDR memory

GPU/NPUs design experience

chiplet architectures / advanced包装

Job description

Are you an RTL Design Engineer looking to take the jump to a hugely-growing AI startup revolutionising accelerator technology? This could be the role for you!

What you'll be doing

• Design and implement RTL for advanced digital and SoC designs.
• Translate architectural requirements into efficient hardware solutions.
• Optimise designs for performance, power, and area.
• Work with verification and implementation teams to deliver high-quality silicon.
• Debug and resolve design issues throughout development and silicon bring-up.
• Contribute to technical reviews and cross-functional engineering discussions.

What you need

• Strong ASIC and SoC design experience
• Deep understanding of AMBA protocols
• Knowledge of high-bandwidth memory systems (HBM, DDR).
• Experience designing high-performance compute engines in GPU or NPU is a plus.
• Familiarity with chiplet architectures or advanced packaging
• Experience with performance modeling and architecture exploration