Senior RTL Architect: High-Speed SerDes DSP Design

Credo; San Jose (CA); On-site; USD 180,000 - 250,000; Full time

Benefits offered by this job

Discretionary bonus

Equity

Medical benefits

Job summary

Credo is seeking a Principal Design Engineer at our San Jose HQ to own RTL architecture, design, implementation, and verification of SerDes DSP blocks for networking, AI, data center, and HPC products.

The ideal candidate has 15+ years in digital design, 10+ years in verification, strong SystemVerilog RTL skills, and experience with ASIC flows and high-speed SerDes. Onsite position with comprehensive compensation and benefits.

Qualifications

• BS/MS/PhD in Electrical Engineering, Computer Engineering, or related field.
• 15+ years of digital design experience.
• 10+ years of block-level/system-level verification experience.
• Proficient in bit-true verification and DPI/PLI verification methodology.
• Strong RTL development skills using System Verilog.

Responsibilities

• Define RTL micro-architecture for digital PHY and SerDes DSP functions.
• Develop synthesizable RTL for DSP blocks (FFE, DFE, MLSD, adaptive equalization, FEC, etc.).
• Work with system architects and algorithm teams to translate DSP algorithms into RTL.
• Optimize designs for performance, power, area, and latency.
• Verify DSP modules and debug functional issues.
• Support synthesis, timing closure, CDC/RDC analysis, and DFT integration.
• Analyze silicon bring-up data with validation teams to resolve issues.
• Support PHY integration and system-level debugging.

Skills

15+ years digital design

10+ years verification

SystemVerilog RTL

High-speed SerDes DSP hardware

Fixed-point RTL

ASIC design flow

EDA tools familiarity

Debugging & problem-solving

Education

BS/MS/PhD in Electrical/Computer Engineering

Tools

Synopsys EDA tools

Cadence EDA tools

Siemens EDA tools

Job description

Credo is seeking a Principal Design Engineer at our San Jose HQ to own RTL architecture, design, implementation, and verification of SerDes DSP blocks for networking, AI, data center, and HPC products.

The ideal candidate has 15+ years in digital design, 10+ years in verification, strong SystemVerilog RTL skills, and experience with ASIC flows and high-speed SerDes. Onsite position with comprehensive compensation and benefits.