Senior Quantum CMOS Analog IC Design Engineer

Global Foundries; Austin (TX); Presencial; USD 143 000 - 275 000; Tempo integral

Resumo da oferta

GlobalFoundries is seeking a Principal Analog Design Engineer to develop advanced analog and mixed-signal ICs and reusable IP for cryogenic CMOS and quantum applications. You will drive designs from architecture through tapeout and silicon validation, partnering with technology, PDK, modeling, layout, and test teams.

Responsibilities include designing high-performance CMOS circuits, leading layout and verification, and collaborating with model and PDK teams to ensure design accuracy across

Qualificações

• Bachelor's degree in Electrical Engineering, Microelectronics, Computer Engineering, Applied Physics, or a related field.

Responsabilidades

• Design high-performance analog and mixed-signal CMOS circuits and reusable IP.
• Lead circuit development from architecture through tapeout and silicon validation.
• Collaborate with device modeling and PDK teams to assess model accuracy and gaps.
• Drive analog layout requirements and reviews for matching, shielding, and power integrity.
• Define silicon test structures and characterization plans; analyze measured data.

Conhecimentos

Analog design

Schematic design

SPICE

Layout supervision

DRC/LVS

Parasitic extraction

Tapeout

Silicon validation

Cryogenic design

Modeling/PDK feedback

Python scripting

Formação académica

Bachelor's degree in Electrical Engineering or related

Master's or PhD (preferred)

Ferramentas

SPICE simulation

Layout editing/verification

Post-layout extraction

Python/Tcl scripting

Descrição da oferta de emprego

GlobalFoundries is seeking a Principal Analog Design Engineer to develop advanced analog and mixed-signal ICs and reusable IP for cryogenic CMOS and quantum applications. You will drive designs from architecture through tapeout and silicon validation, partnering with technology, PDK, modeling, layout, and test teams.

Responsibilities include designing high-performance CMOS circuits, leading layout and verification, and collaborating with model and PDK teams to ensure design accuracy across