Senior Cryogenic CMOS Analog Design Engineer

GlobalFoundries inc.; Austin, Northern (TX, KY); Hybrid; USD 118,000 - 275,000; Full time

Job summary

GlobalFoundries is seeking a Senior Analog Design Engineer to develop high-performance analog and mixed-signal ICs, including cryogenic CMOS designs for quantum systems. You will drive designs from architecture through tapeout, coordinating with technology, PDK, modeling, and test teams.

Responsibilities include robust circuit analysis across process, voltage, and temperature, extensive layout supervision, and validation with silicon characterization.

Qualifications

• Bachelor’s degree in Electrical Engineering, Microelectronics, Computer Engineering, Applied Physics, or a related field.
• Minimum 5 years of analog or mixed-signal IC design experience.
• Experience taking analog or mixed-signal circuits through schematic design, simulation, layout, DRC/LVS, tapeout, and silicon validation.
• Strong knowledge of CMOS analog design fundamentals, including device physics, noise, matching, feedback, stability, and PVT/Monte Carlo analysis.

Responsibilities

• Design and develop high-performance analog and mixed-signal CMOS circuits and reusable IP.
• Own circuit development from architecture through tapeout and silicon validation.
• Collaborate with modeling, PDK, test teams and drive design reviews.
• Define silicon test structures, analyze data, and debug issues across temp ranges including cryogenic conditions.
• Mentor engineers and coordinate with cross-functional teams to enable solutions.

Skills

Analog IC design

CMOS analog design

SPICE simulation

Layout supervision

Test and validation

DRC LVS

Python scripting

Cryogenic temperatures

Education

Bachelor's degree in Electrical Engineering

Tools

SPICE

Cadence Virtuoso

DRC LVS tools

Python

Job description

GlobalFoundries is seeking a Senior Analog Design Engineer to develop high-performance analog and mixed-signal ICs, including cryogenic CMOS designs for quantum systems. You will drive designs from architecture through tapeout, coordinating with technology, PDK, modeling, and test teams.

Responsibilities include robust circuit analysis across process, voltage, and temperature, extensive layout supervision, and validation with silicon characterization.