Senior/Principal Hardware ASIC Validation Engineer

Draper; Odon (IN); On-site; USD 82,300 - 220,000; Full time

Job summary

Draper is hiring a Senior Analog ASIC Validation Engineer in Odon, Indiana. The successful candidate will define, design, verify, and validate ASICs and mentor junior engineers. A bachelor's degree in engineering and significant experience in integrated circuit design is required. Ideal candidates will possess skills in analog and mixed-signal products, along with project management abilities. The expected salary ranges between $82,300 and $220,000, commensurate with experience. The position offers a dynamic and collaborative work environment with opportunities for innovation.

Qualifications

• Requires 5-7 years of experience with a bachelor’s degree in ASIC Hardware Engineering.
• Experience with low-power circuit design is preferred.
• Experience with CMOS advanced nodes below 32 nm is a plus.

Responsibilities

• Specify, design, verify, and validate ASICs with detailed test plans.
• Develop, document, and teach best practices to junior engineers.
• Manage and maintain project schedules aligning with product releases.

Skills

Integrated circuit design

Understanding of semiconductors

Project management skills

Excellent communication skills

Analytical and problem-solving skills

Education

Bachelor’s degree in Engineering

Master’s degree preferred

Job description

Overview

Draper is an independent, nonprofit research and development company headquartered in Cambridge, MA. The 2,000+ employees of Draper tackle important national challenges with a promise of delivering successful and usable solutions. From military defense and space exploration to biomedical engineering, lives often depend on the solutions we provide. Our multidisciplinary teams of engineers and scientists work in a collaborative environment that inspires the cross‑fertilization of ideas necessary for true innovation.

Job Description Overview

A Senior Analog ASIC Validation Engineer specifies, designs, verifies, tests and validates on the bench and documents Application‑Specific Integrated Circuits.

Responsibilities

• The candidate will be involved in every phase of product development from inception to first silicon bring‑up, through correlation, characterization, qualification, release to manufacturing and throughout the life cycle of the product.
• The ideal candidate will be technically strong and will have experience with both Analog and Mixed‑Signal products.
• The candidate will have the opportunity to mentor and train junior engineers.
• Generation of detailed test plans guaranteeing EC table performance and functionality.
• Early collaboration with design to implement testability features to optimize cost and improve quality.
• Develop innovative, cost‑efficient, and manufacturable wafer‑level and IC test solutions on high performance analog & mixed‑signal ATE platforms.
• Execute all phases of the development process including silicon debug, correlation, characterization, limit generation, yield analysis and offshore production transfer.
• Schematic design, layout supervision, component procurement and assembly supervision of multi‑site ATE HW for precision analog amplifiers and mixed‑signal ICs.
• Perform characterization data analysis using statistical methodologies for silicon characterization.
• Design and develop high performance test solutions on products for first silicon verification, characterization, qualification, and manufacturing of precision digital and mixed‑signal products.
• Define test schematics and work with layout engineers to design printed circuit boards for multi‑site test hardware.
• Debug test programs, correlate production test solutions to engineering bench measurements, and transfer production test solutions to manufacturing sites.
• Participate in new product development teams and evaluate new test systems for future applications.
• Work with the Design and Systems/Applications teams to develop and implement a Design for Test plan, and take tests in the Design Verification environment to the Automatic Test Equipment.
• Manage and maintain project schedules that align with product introduction and release.

Duties / Responsibilities

• Design and simulate circuits at transistor‑level to implement architecture and requirement specifications.
• Contribute to system‑level design.
• Optimize hardware designs for performance, power, and cost.
• Evaluate the hardware feasibility of complex algorithms and requirements.
• Independently contribute to complex chip architectures and designs.
• Independently drive solutions to complex problems – develop requirements, propose ways forward when customer requirements are unclear or incomplete, and adapt appropriately to changes in requirements.
• Contribute to business development and proposal activities.
• Develop, document, and teach best practices to less experienced engineers.
• Perform or guide physical layout, including floor‑planning, and simulate circuits using extracted parasitics.
• Perform other duties as assigned.

Skills / Abilities

• Proficiency in integrated circuit design.
• Understanding of integrated circuits, semiconductors, and general computer architecture.
• Ability to write detailed design specifications.
• Ability to manage small technical teams.
• Excellent verbal and written communication skills.
• Excellent mathematical skills.
• Excellent organizational skills and attention to detail.
• Excellent time management skills with the proven ability to meet deadlines.
• Strong analytical and problem‑solving skills.
• Ability to prioritize tasks.
• Demonstrate strong organization, planning, and time management skills to achieve program goals.

Education

• Requires a bachelor’s degree in Engineering, or related field. Master’s degree preferred.

Experience

• Requires 5‑7 years of experience with a bachelor’s degree, or 3‑5 years of experience with a master’s degree, or 0‑2 years of experience with a PhD in ASIC Hardware Engineering or related.

Preferred Qualifications

• Experience with low‑power circuit design.
• Experience with CMOS advanced nodes below 32 nm.
• Experience with radiation‑hardened electronics.

Location

Cambridge, Massachusetts 02139‑3563

Compensation

US base salary range: $82,300.00 – $220,000.00. The range reflects the minimum and maximum target salaries for the position across all US locations.

EEO Statement

Draper is committed to creating an inclusive environment. We understand the value of inclusivity and its impact on a high‑performance culture. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, disability, age, sexual orientation, national origin, veteran status, or genetic information. Draper is committed to providing access, equal opportunity, and reasonable accommodation for individuals with disabilities in employment. To request reasonable accommodation, please contact [e-mail].