Senior/Principal Hardware ASIC Validation Engineer

Draper Labs; Cambridge (MA); On-site; USD 82,300 - 220,000; Full time

Job summary

Draper Labs in Cambridge, Massachusetts is hiring a Senior Analog ASIC Validation Engineer. This role involves specifying, designing, and validating integrated circuits through all phases of product development. Candidates should have a bachelor's degree in Engineering, with 5-7 years of experience. Responsibilities include mentorship, designing test solutions, and collaboration with cross-functional teams. The base salary is between $82,300.00 – $220,000.00 annually, depending on experience.

Qualifications

• Requires 5-7 years of experience with a bachelor's degree in ASIC Hardware Engineering.
• Requires experience with Analog and Mixed-Signal products.
• Proficiency in writing detailed design specifications.

Responsibilities

• Involved in every phase of product development from inception to first silicon bring-up.
• Mentor and train junior engineers.
• Develop innovative IC test solutions on high-performance platforms.

Skills

Integrated circuit design

Excellent verbal and written communication skills

Strong analytical and problem-solving skills

Excellent organizational skills

Time management skills

Education

Bachelor's degree in Engineering or related field

Master’s degree preferred

Job description

Overview:

Draper is an independent, nonprofit research and development company headquartered in Cambridge, MA. The 2,000+ employees of Draper tackle important national challenges with a promise of delivering successful and usable solutions. From military defense and space exploration to biomedical engineering, lives often depend on the solutions we provide. Our multidisciplinary teams of engineers and scientists work in a collaborative environment that inspires the cross‑fertilization of ideas necessary for true innovation.

Job Description Summary:

A Senior Analog ASIC Validation Engineer specifies, designs, verifies, tests, and validates Application‑Specific Integrated Circuits. They are involved in every phase of product development from inception to first silicon bring‑up, through correlation, characterization, qualification, releasing to manufacturing, and throughout the entire life cycle of the product.

Responsibilities:

• The candidate will be involved in every phase of product development from inception to first silicon bring‑up, through correlation, characterization, qualification, release to manufacturing, and throughout the life cycle of the product.
• The ideal candidate will be technically strong and will have experience with both Analog and Mixed‑Signal products.
• The candidate will have the opportunity to mentor and train junior engineers.
• Generation of detailed test plans guaranteeing EC table performance and functionality.
• Early collaboration with design to implement testability features to optimize cost and improve quality.
• Develop innovative, cost‑efficient, and manufacturable wafer‑level and IC test solutions on high‑performance analog & mixed signal ATE platforms.
• Execute all phases of the development process including silicon debug, correlation, characterization, limit generation, yield analysis, and offshore production transfer.
• Schematic design, layout supervision, component procurement and assembly supervision of multi‑site ATE HW for precision analog amplifiers and mixed signal ICs.
• Perform characterization data analysis using statistical methodologies for silicon characterization.
• Design and develop high‑performance test solutions on products for first silicon verification, characterization, qualification, and manufacturing of precision digital and mixed signal products.
• Define test schematics and work with layout engineers to design printed circuit boards for multi‑site test hardware.
• Debug test programs, correlate production test solutions to engineering bench measurements, and transfer production test solutions to manufacturing sites.
• Participate in new product development teams and evaluate new test systems for future applications.
• Work with the Design and Systems/Applications teams to develop and implement a Design for Test plan, and take tests in the Design Verification environment to the Automatic Test Equipment.
• Manage and maintain project schedules that align with product introduction and release.
• Design and simulate circuits at transistor‑level to implement architecture and requirement specifications.
• Contribute to system‑level design.
• Optimize hardware designs for performance, power, and cost.
• Evaluate the hardware feasibility of complex algorithms and requirements.
• Independently contribute to complex chip architectures and designs.
• Independently drive solutions to complex problems – develop requirements, propose ways forward when customer requirements are unclear or incomplete, and adapt appropriately to changes in requirements.
• Contribute to business development and proposal activities.
• Develop, document, and teach best practices to less experienced engineers.
• Perform or guide physical layout, including floor‑planning, and simulate circuits using extracted parasitics.
• Perform other duties as assigned.

Skills/Abilities:

• Proficiency in integrated circuit design.
• Understanding of integrated circuits, semiconductors, and general computer architecture.
• Ability to write detailed design specifications.
• Ability to manage small technical teams.
• Excellent verbal and written communication skills.
• Excellent mathematical skills.
• Excellent organizational skills and attention to detail.
• Excellent time management skills with the proven ability to meet deadlines.
• Strong analytical and problem‑solving skills.
• Ability to prioritize tasks.
• Demonstrate strong organization, planning, and time management skills to achieve program goals.

Education:

• Requires a bachelor's degree in Engineering, or related field. Master’s degree preferred.

Experience:

• Requires 5‑7 years of experience with a bachelor’s degree, or 3‑5 years of experience with a master’s degree, or 0‑2 years of experience with a PhD in ASIC Hardware Engineering or related.

Preferred Qualifications:

• Experience with low power circuit design.
• Experience with CMOS advanced nodes below 32nm.
• Experience with radiation‑hardened electronics.

Applicants selected for this position will be required to obtain and maintain a government security clearance.

Job Location:

Cambridge, Massachusetts 02139-3563

Salary:

US base salary range for this full‑time position: $82,300.00 – $220,000.00.

Equal Opportunity Employer:

Draper is committed to creating an inclusive environment. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, disability, age, sexual orientation, national origin, veteran status, or genetic information. Draper is committed to providing access, equal opportunity, and reasonable accommodation for individuals with disabilities in employment, its services, programs, and activities. To request reasonable accommodation, please contact [e-mail].