Senior Principal Digital IC Design & Architecture Lead

Analog Devices, Inc.; Colorado Springs (CO); On-site; USD 157,080 - 227,460; Full time

Job summary

Analog Devices, Inc. is hiring a Principal Engineer for Digital IC Design and Architecture in Beaverton, OR or Colorado Springs, CO.

You will architect, design, and verify high-speed SerDes blocks and subsystems for next‑gen automotive connectivity solutions. You will drive OpenGMSL technology evolution, author technical standards, and lead cross-functional design reviews while supporting silicon bring-up and debugging.

Qualifications

• MSEE or Equivalent required with 7+ years of relevant experience, or PhD with 4+ years of relevant experience.
• Digital Design experience using Verilog/SystemVerilog is required.
• System architecture and implementation experience at the chip level is needed.
• Strong communication skills and team collaboration are essential.
• SerDes and high-speed video/data transport knowledge is required.
• Experience with timing analysis, power estimation, physical design, and DFT concepts is desirable.
• Hands-on silicon bring-up, lab debugging, and test activities are valued.

Responsibilities

• Architect and design digital blocks and subsystems for high-speed SerDes ICs.
• Drive OpenGMSL technology evolution and participate in standards bodies.
• Write block/subsystem specifications and lead RTL, verification, and top-level design.
• Collaborate across analog/digital/verification/test product teams to ensure product success.
• Lead architecture/design reviews and support silicon bring-up and debug.

Skills

Verilog/SystemVerilog

System Architecture

Communication Skills

SerDes & Video/Data Transport

Timing/Power/Physical Considerations

Lab/Debug Experience

DFT Concepts

Proven Track Record

Matlab

Education

MSEE or Equivalent

PhD (preferred)

Job description

Analog Devices, Inc. is hiring a Principal Engineer for Digital IC Design and Architecture in Beaverton, OR or Colorado Springs, CO.

You will architect, design, and verify high-speed SerDes blocks and subsystems for next‑gen automotive connectivity solutions. You will drive OpenGMSL technology evolution, author technical standards, and lead cross-functional design reviews while supporting silicon bring-up and debugging.