Senior/Principal Digital Design Engineer

ZipRecruiter; Salt Lake City (UT); On-site; USD 100,000 - 130,000; Full time

Job summary

Join a leading technology firm that blends startup spirit with corporate stability. As part of our team, you will tackle complex problems and design secure system solutions for military and critical infrastructure. Your role will involve collaborating with leaders, developing microarchitectures, and mentoring junior engineers. We offer competitive pay, flexible schedules, and a range of benefits, including health insurance and retirement contributions.

Benefits

Competitive Pay

Flexible Work Schedule

Health Benefits and Insurance

Retirement fund contributions

Profit Sharing

Generous Paid Time Off Policy

Qualifications

• At least 5 years of FPGA or ASIC product development experience.
• Proven ASIC design and fabrication experience.

Responsibilities

• Collaborate with team leaders to identify real problems and solutions.
• Develop and define the microarchitecture of new Idaho Scientific IP.

Skills

Communication

Analytical Skills

Problem-Solving

Team Collaboration

Education

Degree in Computer or Electrical Engineering

Tools

SystemVerilog

VHDL

Job description

Job Description

Life is Short. Solve Hard Problems with Cool People.

Idaho Scientific is the Goldilocks of technology firms, combining the spirit and growth of a startup with the financial stability of a large corporation. Our benefits include:

• Competitive Pay
• Flexible Work Schedule
• Health Benefits and Insurance
• Retirement fund contributions
• Profit Sharing
• Generous Paid Time Off Policy

Solve the Problem, Not the Symptom.

We design and deploy secure system solutions through novel CPU design, crypto cores, purpose-built system-on-a-chip architectures, and hardened operating systems. Our solutions support military systems and US critical infrastructure to remain safe and secure in unpredictable environments.

What You'll Get To Do:

• Collaborate with team leaders to identify real problems and solutions.
• Develop and define the microarchitecture of new Idaho Scientific IP to optimize performance, I/O, power, area, cost, and security.
• Implement and simulate IP blocks in RTL using SystemVerilog, VHDL, and other tools.
• Integrate complex systems with Idaho Scientific and third-party IP.
• Contribute to all design phases from specification to production.
• Apply our IP to ASIC and FPGA products.
• Improve design methods and processes.
• Mentor and guide other ASIC design engineers.

Required Qualifications & Experience:

• US Citizenship (no exceptions)
• Proven ASIC design and fabrication experience
• Ability to obtain a security clearance
• At least 5 years of FPGA or ASIC product development experience
• Strong communication skills
• Degree in Computer or Electrical Engineering or related field
• Deep knowledge of digital architectures, RTL coding, synthesis, and verification
• Strong analytical and problem-solving skills
• Attention to detail
• Willingness to work hands-on
• Effective team collaboration skills

Additional Qualifications & Experience:

• Active or recent US Security Clearance
• Understanding of microprocessor architectures
• Knowledge of cryptography and cybersecurity
• Experience with SystemVerilog, VHDL, and TDD

Location:

• Boise, Idaho or Salt Lake City, Utah

Commitment:

Idaho Scientific is an equal opportunity employer. We do not discriminate based on race, creed, color, religion, gender, citizenship, ancestry, marital status, veteran status, medical condition, or any protected category by law.

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