Senior Principal C++ Software Engineer

Cadence; San Jose (CA); On-site; USD 154,000 - 286,000; Full time

Benefits offered by this job

401(k) plan with employer match

Employee stock purchase plan

Medical, dental, and vision plan options

Paid vacation and holidays

Job summary

Cadence in San Jose, California is seeking an experienced C++ software engineer to join the Protium Software Development Team. You will work on FPGA-based prototyping products used for software validation in collaboration with leading CPU/GPU companies. The position involves enhancing timing algorithms and improving product features.

Applicants should have significant experience in EDA software development, and excellent programming skills in C/C++. The role offers a competitive salary range of $154,000 to $286,000 along with benefits such as paid vacation and a 401(k) plan.

Qualifications

• Experience in EDA software development is essential.
• Strong programming skills in C/C++ required.
• Knowledge of multi-threaded/concurrent programming is a plus.

Responsibilities

• Enhance and support Timing Engine with new features.
• Support Timing Flow for improved compile time.
• Design and innovate timing graph algorithms.

Skills

C/C++ programming

SDC constraints

Timing Analysis

Multi-threaded programming

Tcl knowledge

Education

BS with 10 years experience or MS with 7 years or PhD with 5 years

Tools

EDA software

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

We are looking for an experienced C++ software engineer to join the Protium Software Development Team to develop and enhance the FPGA-Based Prototyping product which is used by leading CPU/GPU/HyperScaler companies for pre-Silicon software validation of their SOC’s.

You will develop new algorithms and optimizations for QoR (Quality of Results) and performance for the Protium Timing flow working with a small team of engineers to develop our next generation FPGA based verification platform.

Responsibilities

• Enhance and support Timing Engine to add new features and extend existing features
• Enhance and support Timing Flow to improve P&R compile time
• The role involves designing, tuning, and innovating timing graph algorithms and flow operating on multi‑billion‑node timing graphs
• Write Specifications and Unit Tests for your code

Position Requirements/Qualifications

• BS with a minimum of 10 years of experience OR MS with a minimum of 7 years of experience OR PhD with a minimum of 5 years of experience
• Experience in EDA software development.
• Strong background in SDC constraints and Timing Analysis
• Excellent programming skills in C/C++
• Strong knowledge of Tcl is preferred
• Experience in multi-threaded/ concurrent programming are pluses.
• Prior experience with Emulation or FPGA software development is an added plus.

The annual salary range for California is $154,000 to $286,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

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