Senior Principal Analog IC Architect

GlobalFoundries; Richardson (TX); On-site; USD 171,000 - 296,000; Full time

Job summary

GlobalFoundries is seeking a Principal Analog Design Engineer to own the architecture and design of high‑performance analog/mixed‑signal IP used across multiple SoCs. The role focuses on signal chain IP (ADC/DAC/amps/interfaces) or power management IP (LDOs/DC‑DCs/bandgaps).

You will lead transistor‑level design, schematic/verification, and collaborate with digital, layout and product teams to ensure robust, scalable IP.

Qualifications

• BS or MS in electrical/computer engineering or related field.
• 16+ years in analog/mixed-signal design with end-to-end IP delivery.
• Deep CMOS analog fundamentals, noise, stability, mismatch and variation.
• Experience with industry EDA tools (Cadence, Synopsys, Ansys).
• Ability to script (Perl/Python) and automate tasks; proficient in Virtuoso.
• Strong debugging, silicon bring-up, and documentation skills.

Responsibilities

• Own architecture and design of high-performance analog/mixed-signal IP.
• Lead schematic, simulation, and verification across PVT corners.
• Collaborate with digital, system, layout, and product teams.
• Drive silicon bring-up, characterization, and IP re-use improvements.
• Define DFT requirements and contribute to test cost reductions.
• Provide mentorship and enforce best practices in analog design.

Skills

Analog/mixed-signal design

CMOS technology nodes

Schematic design & verification

Lab debugging & instrumentation

System-level thinking & noise analysis

Cross-functional collaboration

Technical leadership & mentoring

Verilog/VHDL familiarity

Documentation & requirements writing

Education

Bachelor’s or Master’s in Electrical/Computer Engineering

Tools

Cadence

Synopsys

Ansys

Virtuoso

Job description

GlobalFoundries is seeking a Principal Analog Design Engineer to own the architecture and design of high‑performance analog/mixed‑signal IP used across multiple SoCs. The role focuses on signal chain IP (ADC/DAC/amps/interfaces) or power management IP (LDOs/DC‑DCs/bandgaps).

You will lead transistor‑level design, schematic/verification, and collaborate with digital, layout and product teams to ensure robust, scalable IP.