Senior Power IC Layout Designer

Texas Instruments; Dallas (TX); On-site; USD 110,000 - 160,000; Full time

Job summary

Texas Instruments seeks an experienced Layout Designer to contribute to power management IC development. The role centers on hands-on layout execution, collaboration with circuit designers, and adopting new tools and flows to push thermal and electrical performance boundaries.

The ideal candidate has deep analog/power layout knowledge, HV rules experience, and proficiency with Cadence Virtuoso and verification flows. On-site role in Texas.

Qualifications

• Deep understanding of analog and power layout techniques (matching, symmetry, current density, electromigration, IR drop management).
• Experience with high-voltage design rules, isolation techniques, and device spacing for BCD/HV processes.
• Knowledge of parasitic-aware layout for sensitive analog blocks (bandgaps, references, comparators, op-amps).
• Familiarity with power device layout (LDMOS, power MOSFETs), bond pads, ESD structures.

Responsibilities

• Collaborate with circuit designers and the design team to deliver high-quality layouts on schedule.
• Communicate clearly within the design environment to coordinate layout efforts.
• Adopt new systems, tools, and processes and contribute to improving team design flows.
• Demonstrate strong analytical and problem-solving skills and drive on-time project delivery.

Education

Associate degree

Tools

Cadence Virtuoso

DRC

LVS

PEX

Parasitic extraction

Job description

Texas Instruments seeks an experienced Layout Designer to contribute to power management IC development. The role centers on hands-on layout execution, collaboration with circuit designers, and adopting new tools and flows to push thermal and electrical performance boundaries.

The ideal candidate has deep analog/power layout knowledge, HV rules experience, and proficiency with Cadence Virtuoso and verification flows. On-site role in Texas.