Lead Layout Design Manager – Power & Analog PMIC

Texas Instruments; Dallas (TX); On-site; USD 140,000 - 190,000; Full time

Job summary

Texas Instruments is seeking a Layout Design Manager to lead a team developing power management ICs for high power density applications. You will own layout execution and drive new tools and flows while collaborating with advanced power packages.

You’ll also mentor engineers and coordinate across design, process, reliability, and packaging teams to ensure on-time delivery. The role emphasizes strong ownership of layout, parasitic-aware design, and partnership with foundry teams to push thermal

Qualifications

• Deep understanding of analog and power layout techniques, including matching, symmetry, current density, electromigration, and IR drop management.
• Experience with high-voltage design rules, isolation techniques, and device spacing for BCD/HV processes.
• Strong knowledge of parasitic-aware layout for sensitive analog blocks such as bandgaps, references, comparators, and op-amps.
• Familiarity with power device layout, including LDMOS, power MOSFETs, bond pads, and ESD structures.
• Proficiency with layout tools such as Cadence Virtuoso and verification flows including DRC, LVS, PEX, and parasitic extraction.
• Knowledge of packaging considerations, including bond wire, flip-chip, and bump layout, as they relate to PMIC layout.

Responsibilities

• Lead a team responsible for layout execution of power management ICs with strong ownership.
• Drive new tools and flows across the layout team and collaborate with design, process and packaging teams.
• Mentor and develop junior layout engineers and manage schedules and resources.
• Interface with circuit designers, product engineers, and foundry partners to ensure on-time delivery.

Skills

Analog layout

Power layout

Parasitic-aware layout

LDMOS layout

Cadence Virtuoso

DRC/LVS/PEX

Cross-functional leadership

Mentoring

Tools

Cadence Virtuoso

Parasitic extraction tools

Job description

Texas Instruments is seeking a Layout Design Manager to lead a team developing power management ICs for high power density applications. You will own layout execution and drive new tools and flows while collaborating with advanced power packages.

You’ll also mentor engineers and coordinate across design, process, reliability, and packaging teams to ensure on-time delivery. The role emphasizes strong ownership of layout, parasitic-aware design, and partnership with foundry teams to push thermal