Layout Designer - PMIC

Texas Instruments; Dallas (TX); On-site; USD 110,000 - 160,000; Full time

Job summary

Texas Instruments seeks an experienced Layout Designer to contribute to power management IC development. The role centers on hands-on layout execution, collaboration with circuit designers, and adopting new tools and flows to push thermal and electrical performance boundaries.

The ideal candidate has deep analog/power layout knowledge, HV rules experience, and proficiency with Cadence Virtuoso and verification flows. On-site role in Texas.

Qualifications

• Deep understanding of analog and power layout techniques (matching, symmetry, current density, electromigration, IR drop management).
• Experience with high-voltage design rules, isolation techniques, and device spacing for BCD/HV processes.
• Knowledge of parasitic-aware layout for sensitive analog blocks (bandgaps, references, comparators, op-amps).
• Familiarity with power device layout (LDMOS, power MOSFETs), bond pads, ESD structures.

Responsibilities

• Collaborate with circuit designers and the design team to deliver high-quality layouts on schedule.
• Communicate clearly within the design environment to coordinate layout efforts.
• Adopt new systems, tools, and processes and contribute to improving team design flows.
• Demonstrate strong analytical and problem-solving skills and drive on-time project delivery.

Education

Associate degree

Tools

Cadence Virtuoso

DRC

LVS

PEX

Parasitic extraction

Job description

Change the world. Love your job.

Texas Instruments is seeking an experienced Layout Designer to join our team! In this role you will be contributing to the development of power management ICs for high power density applications. This role centers on strong hands-on layout execution, close collaboration with circuit designers and the design team, and contributing to the adoption of new tools and flows. You'll help push the boundaries of thermal and electrical performance in cutting-edge power solutions.

Minimum requirements:

• Associate degree
• Minimum 5 years of experience.

Technical qualifications

• Deep understanding of analog and power layout techniques, including matching, symmetry, current density, electromigration, and IR drop management
• Experience with high-voltage design rules, isolation techniques, and device spacing for BCD/HV processes
• Strong knowledge of parasitic-aware layout for sensitive analog blocks such as bandgaps, references, comparators, and op-amps
• Familiarity with power device layout, including LDMOS, power MOSFETs, bond pads, and ESD structures
• Proficiency with layout tools such as Cadence Virtuoso and verification flows including DRC, LVS, PEX, and parasitic extraction

Collaboration and execution qualifications

• Ability to work closely with circuit designers and the design team to deliver high-quality layouts on schedule
• Strong verbal and written communication skills within the design environment
• Ability to adopt new systems, tools, and processes and contribute to improving team design flows
• Demonstrated analytical and problem-solving skills, with the ability to collaborate effectively within the team
• Strong time management and ownership, with the ability to take initiative and drive on-time project delivery