Senior Power Delivery Engineer for HPC GPUs

AMD; Austin (TX); On-site; USD 120,000 - 180,000; Full time

Job summary

AMD is seeking an engineer to design and verify power delivery networks for high-performance CPUs/GPUs/APUs in Austin. You will work with SoC architects and lab teams to ensure robust PDN performance, optimize impedance, and guide layout choices for reliable operation across AMD platforms.

The role emphasizes cross-functional collaboration, mentorship of junior engineers, and hands-on validation using lab equipment and simulations.

Qualifications

• Proven understanding of power supply architectures and PDN in servers and PCIe environments.
• Experience with multi-phase buck regulators and analog/digital control.
• PCB design expertise and ability to guide layout.
• Familiarity with PDN verification, lab measurements, and test plans.

Responsibilities

• Support architecture, design, analysis, and verification of power systems for CPU/GPU/APU power delivery.
• Collaborate with cross-functional teams to design full PDN and validate impedance and droop targets.
• Develop test plans with Board Validation for system-level design margins.
• Mentor junior power engineers in design and validation.

Skills

Power delivery architectures

PDN design in servers/PCIe

Multi-phase buck regulators

Digital PWM controllers

PCB design

Schematic capture

OrCAD/Allegro

High frequency magnetics design

Lab measurements (oscilloscope, eload,

Analog circuit modeling (PSpice/HSpice

SMVIx power management interface

Communication skills

Education

Bachelor’s or Master’s degree in Electrical Engineering

Tools

OrCAD

Allegro

PowerDC/PowerSI/SiWave

Job description

AMD is seeking an engineer to design and verify power delivery networks for high-performance CPUs/GPUs/APUs in Austin. You will work with SoC architects and lab teams to ensure robust PDN performance, optimize impedance, and guide layout choices for reliable operation across AMD platforms.

The role emphasizes cross-functional collaboration, mentorship of junior engineers, and hands-on validation using lab equipment and simulations.