Senior Datacenter GPU Power & Performance Architect

AMD; Austin (TX); On-site; USD 150,000 - 210,000; Full time

Benefits offered by this job

AMD benefits at a glance

Job summary

AMD is seeking a skilled engineer to lead power-constrained performance modeling for Instinct AI/ML/HPC accelerators, guiding target setting across concept to post-launch. You will partner with architecture, SOC design, CAD, foundry, and software teams to optimize power and performance.

You will mentor engineers, drive post-Si calibration, and contribute to workload power analysis while communicating results to executives.

Qualifications

• Background in Computer Architecture, Processor/Accelerator development.
• Experience in Power/Performance projections, modeling and optimization at SoC or System level.
• Familiarity with digital logic physical design and power management techniques (clock gating, power gating, V-F curves, p-states, on-die voltage regulation, clock integrity, etc.).
• Familiarity with post-silicon power/performance debug, model correlation.
• Fluency in communicating with various engineering teams, business leads and executive management.
• Knowledge of DL/ML/LLM/MoE workloads will be a bonus.

Responsibilities

• Own power-constrained performance modeling, projections and target setting from concept to product launch for AMD Instinct accelerators.
• Define product configurations, capabilities and P&P targets with business units and architecture.
• Lead cross-functional P&P attainment with SOC architecture, system, IP, circuit, foundry, CAD and software teams.
• Roll-up Power/Performance readouts and present to executives; drive power efficiency improvements.
• Mentor junior engineers and develop methods for PPA in several SoC stages and workloads.

Skills

Computer Architecture

Power/Performance projections

Digital logic power techniques

Post-silicon power/debug

Cross-functional communication

DL/ML/LLM workloads knowledge

Education

Bachelor’s or Master’s in CS/CE/EE

Job description

AMD is seeking a skilled engineer to lead power-constrained performance modeling for Instinct AI/ML/HPC accelerators, guiding target setting across concept to post-launch. You will partner with architecture, SOC design, CAD, foundry, and software teams to optimize power and performance.

You will mentor engineers, drive post-Si calibration, and contribute to workload power analysis while communicating results to executives.