Senior PMTS ASIC Digital Design Architect

GlobalFoundries inc.; Santa Clara, Northern (CA, KY); Hybrid; USD 167,000 - 275,000; Full time

Job summary

GlobalFoundries in Santa Clara is seeking a PMTS ASIC Digital Design Engineer to lead architecture implementation, microarchitecture development, and RTL design for high-performance processor cores and subsystem components.

You will collaborate with architecture, verification, physical design, DFT, firmware, and software teams to deliver competitive processor products meeting performance, power, area and schedule targets across complex SoC programs.

Qualifications

• Bachelor's or master's degree in electrical engineering, computer engineering, or related field.
• 12+ years of experience in processor, CPU, DSP, or complex SoC digital design.
• Deep understanding of processor microarchitecture, including pipeline design, cache architectures, branch prediction, memory hierarchy, MMU/TLB designs, interrupt handling, coherency protocols.
• Expert-level RTL design experience using Verilog/SystemVerilog.
• Strong understanding of synthesis, timing analysis, CDC, RDC, and low-power design techniques.
• Experience with industry-standard EDA tools and design flows.

Responsibilities

• Develop and implement microarchitecture for CPU cores, cache subsystems, MMU, interconnects, and system controllers.
• Translate architectural specifications into high-quality RTL designs using Verilog/SystemVerilog.
• Define and review detailed design specifications, block-level architectures, and implementation strategies.
• Drive performance optimization, power reduction, and area-efficient design methodologies.
• Analyze and resolve complex design trade-offs involving latency, throughput, and scalability.
• Lead critical processor design initiatives across multiple functional blocks.
• Mentor junior and senior engineers on microarchitecture, RTL coding practices, and design methodologies.
• Conduct architecture, microarchitecture, and RTL design reviews.
• Establish design guidelines and best practices across the organization.
• Influence roadmap and technology decisions for future processor generations.
• Partner with architects to evaluate new features and enhancements.
• Work closely with verification teams to define verification plans and close coverage.
• Support synthesis, timing closure, low-power implementation, and physical design activities.
• Collaborate with DFT teams to ensure manufacturability and testability.
• Support silicon bring-up, debug, characterization, and production ramp activities.
• Conduct design performance analysis and bottleneck identification.
• Drive microarchitectural enhancements to improve IPC, memory latency, and system efficiency.
• Analyze workload behavior and benchmark performance.
• Participate in power-performance-area (PPA) optimization efforts.

Skills

Processor microarchitecture

RTL design

Verilog/SystemVerilog

Synthesis & timing analysis

Debugging & problem solving

Technical leadership

Education

Bachelor's or master's degree in electrical/computer engineering or related field

Tools

Synthesis tools

Timing analysis tools

EDA tool suites

Job description

GlobalFoundries in Santa Clara is seeking a PMTS ASIC Digital Design Engineer to lead architecture implementation, microarchitecture development, and RTL design for high-performance processor cores and subsystem components.

You will collaborate with architecture, verification, physical design, DFT, firmware, and software teams to deliver competitive processor products meeting performance, power, area and schedule targets across complex SoC programs.