Senior ASIC Digital Design Engineer: Processor RTL & IP

GlobalFoundries; Santa Clara (CA); On-site; USD 167,000 - 275,000; Full time

Job summary

GlobalFoundries in Santa Clara, CA is seeking a PMTS Digital Design Engineer to drive architecture implementation, microarchitecture development, and RTL design of high-performance processor cores and subsystems.

You will partner with architecture, verification, physical design, DFT, firmware, and software teams to meet performance, power, area, and schedule targets, and mentor engineers while shaping next-generation processors.

Qualifications

• Bachelor's or master's degree in electrical engineering, Computer Engineering, or related field.
• 12+ years of experience in processor/CPU/DSP/SoC digital design.
• Expert RTL design experience using Verilog/SystemVerilog.
• Strong understanding of synthesis, timing analysis, CDC/RDC, and low-power design techniques.
• Experience with industry-standard EDA tools and design flows.
• Strong debugging and problem-solving skills.

Responsibilities

• Lead architecture implementation, microarchitecture development, and RTL design of high-performance cores and subsystems.
• Collaborate with architecture, verification, physical design, DFT, firmware, and software teams to meet targets.
• Drive performance, power, and area optimization.
• Review designs, establish guidelines, and mentor engineers.
• Support silicon bring-up, characterization, and production ramp activities.
• Conduct design reviews and contribute to roadmaps.

Skills

Processor/SoC design

RTL design

Synthesis & timing analysis

EDA tools & design flows

Debugging & problem solving

Microarchitecture knowledge

Education

Bachelor's or Master's in Electrical/Computer Engineering

Job description

GlobalFoundries in Santa Clara, CA is seeking a PMTS Digital Design Engineer to drive architecture implementation, microarchitecture development, and RTL design of high-performance processor cores and subsystems.

You will partner with architecture, verification, physical design, DFT, firmware, and software teams to meet performance, power, area, and schedule targets, and mentor engineers while shaping next-generation processors.