PMTS ASIC Digital Design IP ENGINEERING

Global Foundries; Santa Clara (CA); On-site; USD 167,000 - 275,000; Full time

Job summary

GlobalFoundries is seeking a PMTS Digital Design Engineer to lead architecture implementation, microarchitecture development, and RTL design of high-performance processor cores and subsystems. You will collaborate with architecture, verification, physical design, DFT, firmware, and software teams to meet performance, power, and area targets.

The role requires expert RTL design skills in Verilog/SystemVerilog, strong leadership, and a track record of driving complex SoC development programs from

Qualifications

• 12+ years in processor, CPU, DSP, or complex SoC digital design.
• Deep understanding of pipeline design, cache architectures, and memory hierarchy.
• Expert RTL design experience using Verilog/SystemVerilog.

Responsibilities

• Lead architecture, microarchitecture, and RTL design of CPU cores and subsystems.
• Translate architectural specs into RTL and review detailed design specs.
• Drive performance, power, and area optimization across SoC blocks.
• Collaborate with verification, physical design, DFT, firmware, and software teams.
• Provide technical leadership and mentoring across multiple teams.

Skills

Processor design

Microarchitecture

Leadership

Mentoring

Problem solving

Education

Bachelor's or master's in electrical or computer engineering

Tools

Verilog/SystemVerilog

Synthesis

Timing analysis

CDC/RDC techniques

Job description

About GlobalFoundries

GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world's most inspired technology companies. With a global manufacturing footprint spanning three continents, GlobalFoundries makes possible the technologies and systems that transform industries and give customers the power to shape their markets. For more information, visit www.gf.com.

Summary of Role

The PMTS Digital Design Engineer will lead the architecture implementation, microarchitecture development, and RTL design of high-performance processor cores and subsystem components. This role requires deep expertise in processor design, strong technical leadership, and the ability to drive complex SoC development programs from concept through silicon bring-up. The candidate will work closely with architecture, verification, physical design, DFT, firmware, and software teams to deliver competitive processor products meeting performance, power, area, and schedule targets.

Essential Responsibilities

• Processor Microarchitecture & RTL Design
  Develop and implement microarchitecture for CPU cores, cache subsystems, memory management units (MMU), interconnects, and system controllers.
• Translate architectural specifications into high-quality RTL designs using Verilog/SystemVerilog.
• Define and review detailed design specifications, block-level architectures, and implementation strategies.
• Drive performance optimization, power reduction, and area-efficient design methodologies.
• Analyze and resolve complex design trade-offs involving latency, throughput, and scalability.
• Technical Leadership
  Lead critical processor design initiatives across multiple functional blocks.
• Mentor junior and senior engineers on microarchitecture, RTL coding practices, and design methodologies.
• Conduct architecture, microarchitecture, and RTL design reviews.
• Establish design guidelines and best practices across the organization.
• Influence roadmap and technology decisions for future processor generations.
• Cross-Functional Collaboration
  Partner with architects to evaluate new features and enhancements.
• Work closely with verification teams to define verification plans and close coverage.
• Support synthesis, timing closure, low-power implementation, and physical design activities.
• Collaborate with DFT teams to ensure manufacturability and testability.
• Support silicon bring-up, debug, characterization, and production ramp activities.
• Performance Analysis & Optimization
  Conduct design performance analysis and bottleneck identification.
• Drive microarchitectural enhancements to improve IPC, memory latency, and system efficiency.
• Analyze workload behavior and benchmark performance.
• Participate in power-performance-area (PPA) optimization efforts.

Other Responsibilities

Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety & Security requirements and programs.

Required Qualifications

• Bachelor's or master's degree in electrical engineering, Computer Engineering, or related field.
• 12+ years of experience in processor, CPU, DSP, or complex SoC digital design.
• Deep understanding of processor microarchitecture, including: Pipeline design, Cache architectures, Branch prediction, Memory hierarchy, MMU/TLB designs, Interrupt and exception handling, Coherency protocols.
• Expert-level RTL design experience using Verilog/SystemVerilog.
• Strong understanding of synthesis, timing analysis, CDC, RDC, and low-power design techniques.
• Experience with industry-standard EDA tools and design flows.
• Strong debugging and problem-solving skills.

Preferred Qualifications

• Experience with RISC-V, ARM, MIPS, ARC, or custom CPU architectures.
• Knowledge of multi-core and heterogeneous computing systems.
• Experience in AI/ML acceleration, vector processing, or advanced computing architectures.
• Experience with performance modeling and architectural simulation.
• Silicon bring-up and post-silicon debug experience.
• Exposure to safety-critical designs (ISO 26262, DO-254) is a plus.

Expected Salary Range

$167,000.00 - $275,000.00

The exact Salary will be determined based on qualifications, experience and location.

Equal Opportunity Statement

GlobalFoundries is fully committed to equal opportunity in the workplace and believes that cultural diversity within the company enhances its business potential. GlobalFoundries goal of excellence in business necessitates the attraction and retention of highly qualified people. Artificial barriers and stereotypic biases detract from this objective and may be illegally discriminatory. All policies and processes which pertain to employees including recruitment, selection, training, utilization, promotion, compensation, benefits, extracurricular programs, and termination are created and implemented without regard to age, ethnicity, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, sexual orientation, gender identity or expression, veteran status, or any other characteristic or category specified by local, state or federal law