Senior ASIC Digital Design & IP Engineer

Global Foundries; Santa Clara (CA); On-site; USD 167,000 - 275,000; Full time

Job summary

GlobalFoundries is seeking a PMTS Digital Design Engineer to lead architecture implementation, microarchitecture development, and RTL design of high-performance processor cores and subsystems. You will collaborate with architecture, verification, physical design, DFT, firmware, and software teams to meet performance, power, and area targets.

The role requires expert RTL design skills in Verilog/SystemVerilog, strong leadership, and a track record of driving complex SoC development programs from

Qualifications

• 12+ years in processor, CPU, DSP, or complex SoC digital design.
• Deep understanding of pipeline design, cache architectures, and memory hierarchy.
• Expert RTL design experience using Verilog/SystemVerilog.

Responsibilities

• Lead architecture, microarchitecture, and RTL design of CPU cores and subsystems.
• Translate architectural specs into RTL and review detailed design specs.
• Drive performance, power, and area optimization across SoC blocks.
• Collaborate with verification, physical design, DFT, firmware, and software teams.
• Provide technical leadership and mentoring across multiple teams.

Skills

Processor design

Microarchitecture

Leadership

Mentoring

Problem solving

Education

Bachelor's or master's in electrical or computer engineering

Tools

Verilog/SystemVerilog

Synthesis

Timing analysis

CDC/RDC techniques

Job description

GlobalFoundries is seeking a PMTS Digital Design Engineer to lead architecture implementation, microarchitecture development, and RTL design of high-performance processor cores and subsystems. You will collaborate with architecture, verification, physical design, DFT, firmware, and software teams to meet performance, power, and area targets.

The role requires expert RTL design skills in Verilog/SystemVerilog, strong leadership, and a track record of driving complex SoC development programs from