Senior Physical Design Engineer - PnR, PPA & Timing

Wipro; Mountain View (CA); On-site; USD 100,000 - 180,000; Full time

Benefits offered by this job

Medical and dental benefits

Disability insurance

Paid time off

Job summary

Wipro is seeking a Physical Design Engineer to lead PD/PNR activities in Mountain View. You will drive block-level implementation from netlist to GDSII, including floorplanning, CTS, routing, power planning, and verification, with emphasis on PPA, timing convergence, and signoff.

The role requires 8–10 years of experience in VLSI physical design, strong debugging skills, and collaboration with RTL/DFT/STA teams. Eligible for Wipro’s broad benefits and equal opportunity employer policy.

Qualifications

• Experience in physical design and PnR at advanced nodes.
• Strong debugging and signoff skills.
• Knowledge of low-power design techniques.

Responsibilities

• Drive block-level physical design from netlist to GDSII.
• Perform floorplanning, power planning, placement, CTS, routing, and verification.
• Optimize for Power, Performance, and Area targets.
• Achieve timing closure across corners and modes.
• Analyze setup/hold, capacitance, and noise violations.
• Maintain timing constraints (SDC) and STA signoff.
• EMIR analysis and closure.
• Collaborate with RTL, DFT, STA, and Signoff teams for tapeout.
• Debug CD/PD issues and drive convergence within schedules.

Skills

Physical Design

PnR flow

Floorplanning

CTS

Routing

Timing Closure

STA

SDC

EMIR

PPA Optimization

Fusion Compiler/ICC2

PrimeTime

Innovus

RedHawk/Voltus

Education

Bachelors or Masters in Electrical/Electronics Engineering

Tools

Synopsys Fusion Compiler/ICC2

PrimeTime

Cadence Innovus

RedHawk/Voltus

Job description

Wipro is seeking a Physical Design Engineer to lead PD/PNR activities in Mountain View. You will drive block-level implementation from netlist to GDSII, including floorplanning, CTS, routing, power planning, and verification, with emphasis on PPA, timing convergence, and signoff.

The role requires 8–10 years of experience in VLSI physical design, strong debugging skills, and collaboration with RTL/DFT/STA teams. Eligible for Wipro’s broad benefits and equal opportunity employer policy.