Physical Design Engineer (PnR / PPA / Timing Closure)

Wipro; Mountain View (CA); On-site; USD 45,000 - 121,000; Full time

Job summary

Wipro is seeking a Physical Design Engineer to drive block-level design from netlist to GDSII with strong PnR, PPA optimization, and timing convergence. Expect hands-on CTS, routing, EMIR, and STA methodologies, collaborating with RTL/DFT teams to ensure successful tapeouts.

Qualifications include BS/MS in EEE, experience across 7nm/5nm nodes, and proficiency with Fusion Compiler/ICC2, PrimeTime, and Innovus. Competitive compensation and full benefits offered.

Qualifications

• Experience in physical design and PnR flow.
• Strong knowledge of PPA optimization and timing convergence.
• Familiarity with industry-standard EDA tools.
• Understanding of low-power design techniques and signoff methodologies.

Responsibilities

• Drive block-level physical design implementation from netlist to GDSII.
• Perform floorplanning, power planning, placement, CTS, routing, and physical verification.
• Optimize designs for Power, Performance, and Area (PPA) targets.
• Achieve timing closure across multiple corners and modes.
• Analyze and resolve setup, hold, transition, capacitance, and noise violations.
• Develop and maintain timing constraints (SDC) and STA signoff methodologies.
• Perform EMIR analysis and closure.
• Collaborate with RTL, DFT, STA, and Signoff teams to ensure tapeout.
• Debug physical design issues and drive design convergence within project schedules.

Skills

Physical Design

PnR flow

Floorplanning

Placement & Optimization

Clock Tree Synthesis

Routing

Timing Closure

STA

Timing Constraints

EMIR Analysis

PPA Optimization

Education

Bachelor's or Master's degree in Electrical/Electronics Engineering

Tools

Synopsys Fusion Compiler / ICC2

PrimeTime

Cadence Innovus

RedHawk / Voltus

Job description

Physical Design Engineer

We are looking for a Physical Design Engineer with strong expertise in Place & Route (PnR), Power-Performance-Area (PPA) optimization, and timing convergence for advanced technology nodes.

Responsibilities

• Drive block-level physical design implementation from netlist to GDSII.
• Perform floorplanning, power planning, placement, clock tree synthesis (CTS), routing, and physical verification.
• Optimize designs for Power, Performance, and Area (PPA) targets.
• Achieve timing closure across multiple corners and modes.
• Analyze and resolve setup, hold, transition, capacitance, and noise violations.
• Develop and maintain timing constraints (SDC) and STA signoff methodologies.
• Perform EMIR (Electromigration & IR Drop) analysis and closure.
• Collaborate with RTL, DFT, STA, and Signoff teams to ensure successful tapeout.
• Debug physical design issues and drive design convergence within project schedules.

Required Skills

• Strong experience in Physical Design and PnR flow.
• Hands-on expertise in:
  • Floorplanning
  • Placement & Optimization
  • Clock Tree Synthesis (CTS)
  • Routing
  • Timing Closure
  • Static Timing Analysis (STA)
  • Timing Constraints (SDC)
  • EMIR Analysis
  • PPA Optimization
• Experience with industry-standard EDA tools such as:
  • Synopsys Fusion Compiler / ICC2
  • PrimeTime
  • Cadence Innovus (optional)
  • RedHawk / Voltus (EMIR)
• Good understanding of low‑power design techniques and signoff methodologies.
• VLSI Physical Place and Route.

Preferred Qualifications

• Bachelor's or Master's degree in Electrical/Electronics Engineering.
• Experience in advanced nodes (7nm/5nm/3nm preferred).
• Strong debugging and problem‑solving skills.
• Experience working with cross‑functional silicon teams.

Experience: 3–5 Years.

The expected compensation for this role ranges from $45,000 to $121,000. Final compensation will depend on various factors, including geographical location, minimum wage obligations, skills, and relevant experience.

Based on the position, the role is also eligible for Wipro's standard benefits including a full range of medical and dental benefits options, disability insurance, paid time off (inclusive of sick leave), and other paid and unpaid leave options.

Applicants are advised that employment in some roles may be conditioned on successful completion of a post‑offer drug screening, subject to applicable state law.

Wipro provides equal employment opportunities to all employees and applicants for employment and prohibits discrimination and harassment of any type without regard to race, color, religion, age, sex, national origin, disability status, genetics, protected veteran status, sexual orientation, gender identity or expression or any other characteristic protected by federal, state, or local laws. Applications from veterans and people with disabilities are explicitly welcome.