Senior Physical Design Engineer

E-Space; Saratoga (CA); On-site; USD 120,000 - 220,000; Full time

Job summary

E-Space is looking for an experienced Physical Design Engineer to lead complex ASIC and SoC designs. With a focus on innovative satellite technology, you'll work with cutting-edge tools like Cadence Innovus. The role requires a minimum of 8 years of experience in physical design, proficiency in scripting with Tcl or Python, and a strong understanding of low-power design techniques. The position offers a competitive salary range from $120,000 to $220,000 annually, commensurate with experience.

Qualifications

• 8+ years of experience in physical design of ASICs or SoCs.
• Deep expertise in Cadence Innovus and familiarity with other P&R tools.
• Strong experience in floorplanning, power planning, placement, CTS, and routing.

Responsibilities

• Lead physical design implementation from floorplanning through GDSII sign-off.
• Collaborate with the STA team to analyze and resolve timing violations.
• Develop and maintain physical design scripts in Tcl/Python.

Skills

Physical design of complex digital ASICs or SoCs

Cadence Innovus

Scripting in Tcl and Python

Low-power design techniques

Timing closure with STA engineers

Tools

Mentor Calibre

Synopsys ICC2

Job description

Ready to make connectivity from space universally accessible, secure and actionable? Then you’ve come to the right place!

E‑Space is bridging Earth and space to enable hyper‑scaled deployments of Internet of Things (IoT) solutions and services. We are building a highly‑advanced low Earth orbit (LEO) space system that will fundamentally change the design, economics, manufacturing and service delivery associated with traditional satellite and terrestrial IoT systems.

We’re intentional, we’re unapologetically curious and we’re 100% committed to innovate space‑based communications and deliver actionable intelligence that will expand global economies, protect space and our planet and enhance our overall quality of life.

WHAT YOU WILL BE DOING:

• Lead physical design implementation from floorplanning through GDSII sign‑off for complex SoC blocks and full‑chip designs
• Perform floorplanning, power planning, placement, clock tree synthesis (CTS), and routing
• Drive physical design closure meeting PPA (Power, Performance, Area) targets across all design corners
• Collaborate with the STA team to analyze and resolve timing violations through ECO‑driven optimization
• Conduct and resolve physical verification (DRC, LVS, ERC) issues in partnership with the signoff team
• Develop and maintain physical design scripts, flows, and automation in Tcl/Python
• Work with foundry process design kits (PDKs) and ensure design rule compliance on advanced nodes
• Support integration of hard macros, memory compilers, and analog IP into top‑level designs
• Analyze and optimize signal integrity, including crosstalk and noise effects
• Contribute to physical design methodology development and mentor junior engineers

WHAT YOU BRING TO THIS ROLE:

• Minimum 8+ years of experience in physical design of complex digital ASICs or SoCs
• Deep expertise in Cadence Innovus, with broad familiarity with other P&R tools such as Synopsys ICC2
• Strong experience in floorplanning, power planning, placement, CTS, and routing for multi‑million gate designs
• Deep knowledge of timing‑driven physical design and working with STA engineers for timing closure
• Experience with physical verification tools (Mentor Calibre, Synopsys ICV) and DRC/LVS debug
• Proficiency in scripting (Tcl, Python) for flow development and automation
• Solid understanding of low‑power design techniques (clock gating, power domains, UPF/CPF)
• Experience with advanced process nodes and associated PDK constraints
• Strong problem‑solving skills and attention to detail in a deadline‑driven environment

BONUS POINTS:

• Experience with 7nm or sub‑7nm process nodes
• Exposure to custom digital or mixed‑signal IC physical design
• Familiarity with signal integrity analysis tools and methodology
• Experience with hierarchical physical design flows for very large SoCs
• Background in satellite, 5G, or IoT chip design

The target base pay for this position is $120,000 – $220,000 annually. The total compensation packaged will be determined by various factors such as your relevant job‑related knowledge, skills, and experience.

This is a full‑time, exempt position, based out of our Saratoga office.

We are redefining how satellites are designed, manufactured and used. If you have experience in LEO satellite component development, design and in‑orbit activities, we will be immediately wow‑ed.

E‑Space is not currently able to provide employment sponsorship for candidates who do not hold work authorization for the location of this role.