Senior PCB Layout Engineer

Espace

Saratoga (CA)

On-site

USD 150,000 - 200,000

Full time

14 days+

Get more replies from employers

Send a job-specific resume in minutes.

Benefits offered by this job

Health and wellness care options

Competitive salaries

Paid holidays

Paid time off

Job summary

Espace is seeking a Senior PCB Layout Engineer to lead the design of high-performance printed circuit boards in Saratoga. This role involves working with complex multi-layer designs and collaborating across teams to ensure manufacturability and reliability.

Ideal candidates should have over 10 years of PCB design experience, expertise in tools like Altium Designer, and a solid understanding of high-speed interfaces.

The position offers a competitive salary and a chance to significantly impact satellite design and development.

Qualifications

10+ years of hands-on PCB layout experience delivering complex designs.
Deep understanding of PCB materials, stackups, and fabrication processes.
Familiarity with advanced PCB fabrication technologies like mSAP and SLP.

Responsibilities

Lead PCB layout architecture for complex multi-layer designs.
Perform component placement optimizing signal integrity.
Create and review stackup drawings and manufacturing data packages.

Skills

Expert-level proficiency in PCB layout tools

Controlled-impedance routing

Signal integrity fundamentals

High-speed interfaces (PCIe, Ethernet)

Education

Bachelor's degree in electrical engineering

Master's degree (preferred)

Tools

Altium Designer

Cadence Allegro

Job description

Senior PCB Layout Engineer

Ready to make connectivity from space universally accessible, secure and actionable? Then you’ve come to the right place! E-Space is bridging Earth and space to enable hyper-scaled deployments of Internet of Things (IoT) solutions and services. We are building a highly-advanced low Earth orbit (LEO) space system that will fundamentally change the design, economics, manufacturing and service delivery associated with traditional satellite and terrestrial IoT systems.

We’re intentional, unapologetically curious and 100% committed to innovate space-based communications and deliver actionable intelligence that will expand global economies, protect space and our planet and enhance our overall quality of life.

The Senior PCB Layout Engineer is responsible for leading the physical implementation of complex, high-performance printed circuit boards from concept through production. This role requires deep expertise in multi-layer, high-speed, RF, and mixed-signal PCB layout, strong ownership of stackup and via architecture decisions, and direct engagement with PCB fabrication and assembly partners to ensure manufacturability, reliability, and cost efficiency.

Responsibilities

Technical Leadership

Lead PCB layout architecture for complex multi-layer designs (10–20+ layers) including high-speed digital, RF, analog, and power circuitry
Define and own stackups, impedance models, and via strategies (through, blind, buried, microvias, backdrilling)
Serve as the DFM authority for layout decisions, balancing electrical performance, cost, yield, and reliability

Advanced PCB Design & Layout

Perform and guide component placement optimizing signal integrity, power integrity, EMI/EMC, thermal, and mechanical performance
Route high-speed serial interfaces, differential pairs, controlled-impedance nets, and sensitive RF/analog signals
Design robust power distribution networks and grounding structures
Apply advanced shielding and isolation techniques for EMI/EMC control

Fabrication & Assembly Interface

Lead DFM/DFA reviews with PCB fabrication and assembly partners
Resolve complex DFM issues related to HDI structures and sequential lamination, via consolidation, backdrilling, drill count reduction, and stackup optimization for yield and cost
Optimize designs for manufacturability, reliability, and volume production

Cross-Functional Collaboration

Work closely with electrical, mechanical, test, and manufacturing engineers throughout the product lifecycle
Support board bring‑up, debug, ECOs, and production transitions
Mentor and technically guide junior PCB layout engineers

Documentation & Process Ownership

Create and review stackup drawings, fabrication notes, assembly notes, and manufacturing data packages (Gerber / ODB++)
Establish, maintain, and enforce PCB layout standards and best practices
Drive continuous improvement in layout quality, DFM compliance, and cost efficiency

Qualifications

10+ years of hands‑on PCB layout experience delivering complex designs from concept to production
Expert‑level proficiency in PCB layout tools such as Altium Designer, Cadence Allegro
Deep understanding of controlled‑impedance routing and signal integrity fundamentals; power integrity, grounding, and EMI/EMC best practices; PCB materials, stackups, and fabrication processes; HDI PCB design, advanced via structures, and manufacturing constraints
Experience with high-speed interfaces (PCIe, Ethernet, DDR, JESD, SERDES); RF and mixed-signal PCB layouts; aerospace, data center, or high‑reliability hardware designs
Bachelor’s degree in electrical engineering, computer engineering, or a related field (Master’s degree is a plus)
Familiarity with advanced PCB fabrication technologies such as mSAP and SLP, including fine‑line routing, small via structures, and associated DFM constraints
Working knowledge of signal and power integrity simulation tools and DFM analysis workflows

Compensation

This is a full‑time, exempt position based out of our Saratoga office. The target base pay for this position is $150,000 – $200,000 annually. The total compensation package will be determined by your relevant job‑related knowledge, skills, and experience.

We are redefining how satellites are designed, manufactured and used—so we’re looking for candidates with passion, deep knowledge and direct experience on LEO satellite component development, design and in‑orbit activities. If that’s your experience, we’ll be immediately wow‑ed.

E‑Space is not currently able to provide employment sponsorship for candidates who do not hold work authorization for the location of this role.

Benefits